Embedded Component Package via Dielectric Encasement
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Solution Overview
Problem
Existing electronic component packages face limitations in size reduction due to the need for flip chip bumps, which are prone to failure from thermal stress, and require additional manufacturing steps and materials, leading to increased costs and vulnerability to stress and breakage.
Innovation Solution
The method involves coupling an electronic component's bond pads directly to electrically conductive vias formed through a dielectric strip, eliminating the need for flip chip bumps and underfill materials, and encasing the component in dielectric material to reduce stress and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chip bumps are used to connect bond pads to substrate traces, then impedance is reduced and package size is minimized, but the bumps are subject to significant thermal stress and fail frequently
Solution Approach 1:
The patent introduces an underfill material as an intermediary substance between the flip chip bumps and the substrate. This underfill material absorbs and distributes the thermal expansion stress, preventing direct stress transmission to the brittle solder bumps. The underfill acts as a stress buffer that maintains the integrity of the bump connections while allowing for thermal cycling, thereby resolving the contradiction between achieving low impedance connections and maintaining connection reliability under thermal stress.
2Reliability
If underfill material is applied between the integrated circuit chip and substrate, then bump failure is minimized, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the underfill material application step with the existing reflow soldering process. The underfill material is applied to the substrate before placing the flip chip, and then both the underfill and the solder bumps are reflowed simultaneously in a single heating cycle. This merging of operations eliminates the need for separate underfill curing steps, reduces manufacturing complexity, and maintains the reliability benefits of the underfill material while simplifying the production process.
3Reliability
If the entire electronic component is mounted above the substrate surface, then connections are vulnerable to stress and breakage, but substrate surface area is wasted and device size increases
Solution Approach 1:
The patent transitions from a two-dimensional surface mounting approach to a three-dimensional embedded approach. The flip chip is recessed into a cavity formed in the substrate, allowing the component to be partially embedded below the substrate surface rather than mounted entirely above it. This dimensional change provides mechanical support and stress distribution in the vertical dimension, reducing connection vulnerability while efficiently utilizing the substrate surface area and reducing the overall device footprint.
Data Source
AI summary
A method of forming an embedded electronic component package includes coupling a substrate to a first dielectric layer, strip, or panel, and forming first electrically conductive vias and traces in the first dielectric layer. A cavity is then formed in the first dielectric layer and an electronic component is attached in the cavity. A second dielectric layer, strip, or panel, is then applied to the first dielectric layer, thereby encasing the electronic component in dielectric. Second via apertures are then formed through the second dielectric layer to expose selected electronic component bond pads and/or selected first electrically conductive vias and traces. The second via apertures are then filled with an electrically conductive material to form second electrically conductive vias electrically coupled to selected bond pads and selected first electrically conductive vias and traces.