Embedded Component Package Structure Using Molding Compound
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Solution Overview
Problem
Conventional dielectric structures in semiconductor embedded in substrate (SESUB) technology are limited by a resin sheet thickness of up to 80 μm, leading to warpage issues when semiconductor chips are thinned to ensure coverage, which complicates subsequent processes and limits the thickness of the dielectric structure.
Innovation Solution
Replacing the conventional resin sheet with a molding compound material that can be thermoformed to achieve a thicker dielectric structure, allowing for increased thickness without thinning the semiconductor chip, and using dry sandblasting to expose electrical pads for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a resin sheet with thickness up to 80 μm is used as the dielectric structure, then the dielectric structure can be manufactured with conventional materials, but the thickness of the dielectric structure is limited and cannot be increased
Solution Approach 1:
The patent changes the material parameter from conventional resin sheet to molding compound, enabling the dielectric structure thickness to exceed 80 μm while maintaining manufacturability through standard molding processes
Solution Approach 2:
The patent uses molding compound as a composite material that combines the properties of dielectric insulation with the ability to be formed into thick structures through molding, overcoming the thickness limitation of conventional resin sheets
2Length of stationary object
If the semiconductor chip is thinned to ensure complete coverage by the resin, then the chip can be fully covered by the dielectric structure, but the chip develops warpage problems that complicate subsequent processes
Solution Approach 1:
By changing the dielectric material to molding compound with superior flow and filling properties, the patent achieves complete chip coverage without thinning the chip, thus preventing warpage and maintaining chip structural integrity
Solution Approach 2:
The molding compound is applied in a molten state that allows it to naturally flow and completely cover the chip surface before solidifying, ensuring complete coverage without the need for preliminary chip thinning
3Reliability
If the dielectric structure thickness is increased beyond 80 μm, then electrical insulation is enhanced, but conventional resin sheets cannot provide sufficient thickness
Solution Approach 1:
The patent employs molding compound as a composite material that inherently provides both the required electrical insulation properties and the capability to be formed into thick structures, simultaneously achieving enhanced insulation and increased thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for a significantly thicker dielectric structure, preventing warpage and enhancing electrical insulation, while maintaining the integrity of the semiconductor chip, thus improving the yield rate and meeting the demands of advanced technologies like 5G communication systems.
Implementation Method 1
A dielectric structure is provided on the carrier to encapsulate the semiconductor chip, and the dielectric structure is thermoformed by a mold
Implementation Method 2
a dry sandblasting is performed on the dielectric structure to form a first opening exposing an electrical pad of the semiconductor chip
Data Source
AI summary
An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.


