Embedded Component Substrate for Semiconductor Footprint Reduction
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices lead to space and cost inefficiencies due to separate packaging and circuit board manufacturing processes, necessitating a solution to reduce the footprint of semiconductor devices on substrates and simplify the associated processes.
Innovation Solution
An embedded component substrate is developed, featuring a semiconductor device with patterned conductive and dielectric layers, where the semiconductor device is embedded within the substrate, reducing physical space and integrating packaging, circuit board manufacturing, and assembly processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are packaged separately and installed on substrates, then the devices can be protected and connected, but the space occupied by both the package and substrate increases
Solution Approach 1:
The patent merges the semiconductor device package with the substrate by embedding the device directly into the substrate structure. The package encapsulant material extends to surround the semiconductor device and integrates with the substrate, eliminating the need for separate packaging and assembly processes while reducing the overall space occupied.
Solution Approach 2:
The semiconductor device is nested within the substrate by embedding it into the package encapsulant material that is integrated with the substrate. The device is positioned within a cavity or recess in the substrate, and the encapsulant material surrounds and integrates with both the device and substrate, creating a nested configuration that reduces footprint.
2Ease of manufacture
If separate packaging, circuit board manufacturing, and assembly processes are performed, then each process can be optimized independently, but additional cost is incurred
Solution Approach 1:
The patent combines packaging, circuit board manufacturing, and assembly into a single integrated process. The substrate is manufactured with embedded cavities or recesses designed to accommodate semiconductor devices, and the package encapsulant material is applied during the same manufacturing cycle, eliminating the need for separate packaging and assembly steps while reducing overall manufacturing cost.
Solution Approach 2:
The substrate is prepared in advance with pre-formed cavities, recesses, or embedded structures during the circuit board manufacturing process. These preliminary structures are designed to accommodate semiconductor devices, so that when devices are added, they are already positioned and prepared for integration, eliminating the need for separate packaging and assembly operations.
3Area of stationary object
If the footprint of semiconductor devices on substrates is reduced, then space efficiency improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent transitions from a two-dimensional surface mounting approach to a three-dimensional embedding approach. The semiconductor device is positioned within a cavity or recess in the substrate, and the package encapsulant material surrounds the device and integrates with the substrate in the vertical dimension. This dimensional change reduces the horizontal footprint while the embedding process is integrated into standard manufacturing techniques.
Data Source
AI summary
An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.


