Embedded Component Device Substrate Integration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge is to reduce the space occupied by semiconductor devices on substrates while simplifying and combining the packaging, circuit board manufacturing, and assembly processes, as current methods incur additional costs and inefficiencies due to separate processes for semiconductor devices and substrates.

Innovation Solution

An embedded component device is developed, featuring an electronic component with a patterned conductive layer, dielectric layer, and conductive via, along with electrical interconnects, which allows for reduced size and integrated manufacturing processes, enabling the semiconductor device to be embedded within the substrate, thereby minimizing space and streamlining production.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If semiconductor devices are packaged separately and assembled on substrates, then electrical connectivity and protection are ensured, but space is occupied by both the semiconductor device package and the substrate, and manufacturing complexity increases

Engineering Contradiction:
Improvefootprint areaVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent merges the semiconductor device and substrate into a single integrated structure where the semiconductor device is embedded within the substrate. The substrate includes integrated circuitry, conductive interconnects, and dielectric layers that directly encapsulate and connect to the semiconductor device, eliminating the need for separate packaging and assembly processes. This integration reduces the overall footprint area while maintaining electrical connectivity and protection functions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor device is nested within cavities formed in the substrate's dielectric layers. The substrate structure contains the semiconductor device, conductive vias, and interconnects in a hierarchical arrangement where smaller components are embedded within larger structural elements. This nesting approach minimizes the external footprint while preserving all necessary functional elements.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If separate packaging and assembly processes are used, then device functionality is maintained, but additional costs are incurred and production time increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent combines multiple discrete manufacturing processes (semiconductor fabrication, packaging, and substrate assembly) into a single integrated manufacturing flow. The substrate is manufactured with embedded cavities and conductive structures that directly accommodate the semiconductor device, allowing all components to be produced and assembled in one continuous process rather than through separate sequential steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate is prepared in advance with pre-formed cavities, conductive vias, and dielectric layers during the substrate manufacturing process itself, before the semiconductor device is placed. This preliminary preparation of the substrate structure eliminates the need for subsequent packaging operations and reduces the number of manufacturing steps required.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9406658B2Embedded component device and manufacturing methods thereof
Publication Date: 2016.08.02 ADVANCED SEMICON ENG INC
  • US9406658B2 patent drawing
  • US9406658B2 patent drawing
  • US9406658B2 patent drawing

AI summary

An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.