Embedded Computing Device Shared Memory Inter-Processor Communication
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Solution Overview
Problem
Embedded multi-processor devices face challenges in enabling processors and their applications to communicate and share data asynchronously and concurrently, particularly in low-power devices where power consumption optimization is crucial.
Innovation Solution
Implementing a shared information space, referred to as a whiteboard, which allows multiple processing units to write and retrieve data, enabling interoperability and data sharing between processors and applications, even when they are running on different devices or servers, using a data interchange protocol and logical memory mapping techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are used to increase computational capacity and enable concurrent task processing, then processing power and functionality are improved, but power consumption increases
Solution Approach 1:
The system dynamically transitions processors between active and hibernation states based on task requirements. The first processor remains active while the second processor hibernates during basic operations, and activates the second processor only when additional computational capacity is needed, making the processing power adaptable rather than static.
Solution Approach 2:
The system changes the operational state parameter of processors between active and hibernation modes. By modifying the power state parameter dynamically, the system optimizes the balance between processing capacity and energy consumption based on real-time computational demands.
2Use of energy by moving object
If processors hibernate to save power, then energy consumption is reduced, but communication and data sharing between processors become more difficult
Solution Approach 1:
The shared memory space is pre-configured and maintained as a persistent communication channel that remains accessible even when processors are in hibernation state. Data structures and protocols are prepared in advance to enable seamless data exchange when processors transition between states, eliminating the need for complex reconfiguration during wake-up.
Solution Approach 2:
The shared memory space acts as an intermediary between processors, allowing data to be stored and retrieved asynchronously. The notification mechanism serves as a mediator that signals when data is available in the shared memory, enabling reliable communication without requiring processors to remain continuously active or synchronized.
3Adaptability or versatility
If a shared memory space is implemented for data sharing between processors, then interoperability is improved, but memory management complexity increases
Solution Approach 1:
The shared memory space is segmented into distinct regions with specific purposes: a notification area for signaling data availability, data storage areas for different types of information, and protocol definition areas. This segmentation organizes the memory management task into manageable segments rather than a monolithic complex system.
Solution Approach 2:
The shared memory space is designed as a universal communication infrastructure that handles multiple functions: data storage, notification signaling, protocol definition, and inter-processor communication. This multi-functional design consolidates what could be separate complex systems into a single versatile memory structure.
Data Source
AI summary
An apparatus and a method is provided that comprises at least one first processing unit configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processing unit, at least one second processing unit configured to run at least a second computer program application capable of further processing at least some information processed in said first processing unit. According to the invention the first and second processing unit are interfaced with a shared information space, whereby a first application running in the first processing unit is configured to enable said first processing unit to write data to said information space, and a second application running in the second processing unit is configured to receive a notification about said data being written to said shared information space, and to enable said second processing unit to retrieve from said information space said data written by said first processing unit for further processing.