Embedded Conductive Layer for Power and Ground Planes in Fo-eWLB
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Solution Overview
Problem
In fan-out embedded wafer-level ball grid array (Fo-eWLB) semiconductor devices, the lack of dedicated power and ground planes limits routing design options, consumes valuable space, and reduces electrostatic discharge (ESD) protection, as all power, signal, and ground traces are routed within a single redistribution layer (RDL).
Innovation Solution
An embedded conductive layer is formed adjacent to the semiconductor die to provide dedicated power and ground planes, allowing for flexible routing and increased ESD protection without the need for additional RDLs, using conductive layers or dummy dies embedded within the encapsulant to create these planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all power, signal, and ground traces are routed within a single redistribution layer (RDL), then the package structure is simplified, but routing design flexibility is limited and ESD protection is reduced
Solution Approach 1:
The patent segments the electrical interconnection functions by separating power/ground traces from signal traces into different conductive layers. The first conductive layer (RDL) handles signals, while the second conductive layer (embedded in encapsulant) handles power and ground, allowing independent optimization of each routing system and improving overall design flexibility.
Solution Approach 2:
The patent adds a vertical dimension to the interconnection architecture by embedding a second conductive layer within the encapsulant material beneath the semiconductor die. This creates a multi-layer stacked configuration that provides additional routing dimensions without increasing the lateral footprint, thereby enhancing routing flexibility.
2Ease of manufacture
If all power, signal, and ground traces are routed within a single redistribution layer (RDL), then manufacturing is simpler, but valuable space is consumed and ESD protection is reduced
Solution Approach 1:
By segmenting power/ground routing from signal routing into separate conductive layers, the patent enables more efficient space utilization. The embedded second conductive layer uses previously unused space within the encapsulant volume, allowing higher I/O counts and denser routing without increasing package footprint.
Solution Approach 2:
The patent embeds the second conductive layer within the encapsulant material, effectively nesting an additional functional layer inside the existing package structure. This nested configuration provides extra routing capacity without increasing the overall package dimensions, as the second conductive layer is hidden within the encapsulant volume.
3Reliability
If dedicated power and ground planes are added, then ESD protection and routing flexibility are improved, but the number of RDLs must increase
Solution Approach 1:
The patent uses the encapsulant material as an intermediary medium to embed the second conductive layer. This approach provides dedicated power and ground planes with improved ESD protection while avoiding the need to increase the number of traditional RDLs, as the embedded layer is integrated within the encapsulant rather than adding to the RDL stack.
Data Source
AI summary
A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.