Embedded Conductive Layers in 3D Semiconductor Packages
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Solution Overview
Problem
The electronics industry faces challenges in miniaturizing integrated circuit (IC) packages to reduce manufacturing costs and enhance performance, particularly in achieving high-density system integration while minimizing power consumption and extending mobile device operating time.
Innovation Solution
A semiconductor package design that includes a substrate, electronic components, conductive layers, and package bodies, where the conductive layers are embedded within the package bodies, reducing thickness and omitting interposers to achieve smaller package sizes and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional IC package structures are used, then manufacturing cost increases with size, but package miniaturization becomes difficult to achieve
Solution Approach 1:
The patent transitions from conventional 2D planar packaging to 3D vertical stacking architecture. Multiple electronic components are stacked in the vertical dimension, connected through through-silicon vias (TSVs) and interlayer conductors. This dimensional change enables high-density integration without increasing lateral footprint, achieving miniaturization while maintaining manufacturing feasibility through established semiconductor fabrication processes.
Solution Approach 2:
The patent implements nested packaging where smaller electronic components and conductive structures are embedded within larger package layers. Conductive layers are embedded within package bodies, and multiple functional layers are nested vertically. This nesting approach maximizes space utilization and achieves compact package size while using standard manufacturing techniques.
2Quantity of substance
If high integration is achieved through multiple packages, then system density improves, but package complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple separate packaging operations into a single integrated 3D stack structure. Multiple electronic components, conductive layers, and package bodies are combined into one unified vertical assembly. This merging reduces the number of discrete packages needed, simplifies inter-package interconnections, and achieves high integration density while managing complexity through monolithic fabrication approaches.
Solution Approach 2:
The patent creates a universal package structure that performs multiple functions simultaneously: electrical interconnection through TSVs and conductive layers, mechanical support through package bodies, and thermal management through the stacked architecture. This multi-functional design achieves high integration density without proportionally increasing complexity, as a single structure fulfills multiple requirements.
3Power
If 3D graphic processing circuits are enhanced for higher performance, then processing capability improves, but power consumption increases
Solution Approach 1:
The patent places 3D graphic processing circuits in close proximity to memory and other functional components through vertical stacking, dramatically reducing inter-component signal transmission distances. This dimensional reorganization minimizes power consumption associated with data transfer while maintaining high processing performance, as the majority of power usage in 3D graphics is often related to memory access and data movement rather than computation itself.
Data Source
AI summary
A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.