Embedded Conductive Loops for 3D IC Defect Detection
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Solution Overview
Problem
Three-dimensional integrated circuits (3D ICs) face challenges in detecting defects within their multiple tiers, which can lead to disconnections and circuit failures due to warping, cracking, or open cracks between tiers, limiting the effectiveness of existing testing methods.
Innovation Solution
A test structure comprising conductive loops or meshes embedded within the tiers, connected by inter-level vias, allows for the detection of defects by measuring resistance values between test pads, enabling the identification of defects and their location within the semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional integrated circuits with multiple stacked tiers are used to improve integration density, then the integration density increases, but the difficulty of detecting defects within the tiers increases
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete tiers (first tier, second tier, third tier, etc.) with distinct conductive loops in each tier. This segmentation allows defects to be localized to specific tiers by measuring resistance across individual loops, making defect detection feasible despite the complex 3D structure.
Solution Approach 2:
The patent introduces inter-level vias as intermediary elements that connect corresponding conductive loops across different tiers. These vias serve as mediators for electrical connection, enabling resistance measurements that can detect defects in intermediate tiers without requiring direct access to internal structures.
2Length of moving object
If through substrate vias are used to connect stacked wafers or dies, then the interconnect length decreases, but the reliability of connections is reduced due to warping, cracking, or open cracks
Solution Approach 1:
The patent incorporates test structures (conductive loops and inter-level vias) during the manufacturing process, before the product is completed and shipped. This preliminary action enables defect detection to occur prior to deployment, allowing defective units to be identified and rejected before they can cause system failures.
Solution Approach 2:
The resistance measurement system provides feedback about the condition of inter-level vias and conductive paths. By measuring resistance values and comparing them against expected ranges, the system can identify deviations that indicate defects, enabling quality control decisions based on actual measured conditions rather than assumptions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed test structure effectively detects defects by providing a means to measure resistance across conductive paths, allowing for the identification of defects and their location, thereby ensuring the integrity of the 3D ICs and preventing failures.
Implementation Method 1
A test structure comprising conductive loops or meshes embedded within the tiers, connected by inter-level vias, allows for the detection of defects by measuring resistance values between test pads
Data Source
AI summary
A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.