Embedded Conductor Semiconductor Package for Low Inductance
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Solution Overview
Problem
Conventional leadframe concepts for inverter power modules are limited by high chip costs and inefficiencies in connecting power switch devices, leading to constraints in power and temperature ratings, switching symmetry, and signal routing capabilities.
Innovation Solution
A semiconductor package design featuring a leadframe with a first and second die pad, connected by an electrical conductor that is fully encapsulated within the package body, allowing for internal phase connection between power switch devices, reducing inductance and enabling more efficient power transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external routing on customer side is used to connect power switch devices, then inductance can be reduced at application level, but device complexity and routing capability constraints increase
Solution Approach 1:
The patent merges the phase connection function into the package body by providing an internal electrical connection between the first and second die pads. This combines the power switch devices and their interconnection into a single integrated package, eliminating the need for external routing while maintaining low inductance through optimized internal trace design.
Solution Approach 2:
The patent introduces an intermediary electrical connection structure within the package body that mediates the phase connection between high-side and low-side switches. This internal connection structure acts as an intermediary element that provides low-inductance connectivity without requiring external PCB routing.
2Ease of manufacture
If copper clip on chip front side is used for phase connection, then phase connection is achieved, but chip cost increases due to necessity of solderable frontside metallizations
Solution Approach 1:
Instead of connecting the phase node from the front side of the chips (which requires expensive solderable metallizations), the patent inverts the connection approach by providing electrical connection from the rear side of the die pads through the package body. This allows use of simpler metallization structures on the chip front side while achieving phase connection through the package substrate.
3Adaptability or versatility
If two single power switch devices are molded next to each other, then half bridge configuration is achieved, but power and temperature ratings are limited
Solution Approach 1:
The patent optimizes the spatial arrangement of the power switch devices within the package body, utilizing three-dimensional positioning and vertical stacking possibilities. By changing the dimensional arrangement from purely lateral placement to incorporating vertical integration, the package achieves better thermal management and higher power ratings while maintaining half bridge functionality.
Data Source
AI summary
A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.