3D Stacked Nonvolatile Memory Device With Embedded Control Gates
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Solution Overview
Problem
Conventional NAND type flash memories face challenges such as reduced drain current controllability, increased interference between gates, leak current, and deteriorated data retention due to miniaturization, while three-dimensionally stacked memories struggle with erasing characteristics and data retention, and floating gate structures are difficult to manufacture and stack effectively.
Innovation Solution
A nonvolatile semiconductor memory device with a memory cell array structure where control gates are embedded on both sides of floating gates via an inter-gate insulating layer, allowing for improved coupling ratio without the complexity of stacked-gate structures, and a manufacturing method that reduces the number of steps and bit cost by rotating cell array layers 90 degrees for collective pattern processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the floating gate electrode is increased to improve coupling ratio, then the coupling ratio is improved, but the aspect ratio is increased causing pattern leaning or collapsing during fabrication
Solution Approach 1:
The patent transitions from a conventional planar floating gate structure to a three-dimensional stacked structure where multiple memory cell layers are vertically arranged. This dimensional change allows the coupling ratio to be improved through vertical stacking without requiring excessive horizontal scaling that would lead to pattern collapsing during fabrication.
Solution Approach 2:
The patent implements a nested structure where control gates are embedded within inter-gate insulating layers that surround floating gates from multiple sides. This nested arrangement enhances the coupling ratio by providing multi-directional control gate coverage while maintaining manufacturable aspect ratios through systematic layering.
2Reliability
If conventional floating gate type memory cell structure is used to accumulate charges, then data retention is improved, but manufacturing and stacking becomes difficult due to EB structure complexity
Solution Approach 1:
The patent segments the memory cell structure into multiple independent layers stacked vertically, with each layer containing semiconductor layers, gate insulating layers, floating gates, and control gates. This segmentation allows for standardized manufacturing of individual layers that can be systematically stacked, reducing overall manufacturing complexity compared to monolithic EB structures.
Solution Approach 2:
The patent moves from two-dimensional planar processing to three-dimensional vertical stacking, enabling improved data retention through enhanced charge accumulation while simplifying manufacturing through repeated patterning and stacking of standardized layers rather than complex single-step EB processing.
3Area of moving object
If miniaturization is pursued to increase integration density, then device size is reduced, but drain current controllability deteriorates due to increased parasitic capacitance and short channel effect
Solution Approach 1:
The patent addresses miniaturization limitations by transitioning to vertical stacking of multiple memory cell layers, thereby increasing integration density without further reducing horizontal dimensions. This approach maintains adequate gate lengths for proper drain current controllability while achieving higher density through the third dimension.
Solution Approach 2:
The embedded control gate structure provides enhanced electrostatic control over the channel by positioning control gates on both sides of floating gates through inter-gate insulating layers. This nested arrangement reduces parasitic capacitance effects and improves short channel effect control even in miniaturized devices.
4Ease of manufacture
If nitride film trap type cell structure is used for easy stacking, then manufacturing ease is improved, but erasing characteristic and data retention deteriorate due to electron trapping in nitride film
Solution Approach 1:
The patent employs composite material structures combining multiple insulating layers (gate insulating layers and inter-gate insulating layers) with floating gate electrodes and control gates. This composite approach enables effective charge trapping for data retention while maintaining manufacturable stacking through systematic layer integration, avoiding the electron trapping issues of pure nitride film structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the coupling ratio, reduces bit cost, and simplifies the manufacturing process by avoiding the Etch Back structure, thus addressing the limitations of miniaturization and data retention in conventional NAND type flash memories.
Implementation Method 1
control gates that face the floating gates via the inter-gate insulating films on both sides of the floating gates
Implementation Method 2
inter-gate insulating layers adjacent to the floating gates
Implementation Method 3
control gates that face the floating gates via the inter-gate insulating films on both sides of the floating gates in the first direction
Data Source
AI summary
A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.