Embedded Controller Memory Error Tracking

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Solution Overview

Problem

Modern semiconductor memory systems face frequent memory errors due to shrinking storage cell sizes, leading to inadequate monitoring and reporting of memory degradation, which hampers timely corrective action and system reliability.

Innovation Solution

An embedded micro-controller with local memory is integrated within the processor to frequently access and record memory reliability information, including error data, supply voltages, and temperatures, allowing for low-threshold interrupts and high-frequency polling without disrupting processor operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional memory error monitoring is used, then system simplicity is maintained, but memory error detection precision and timeliness deteriorate

Engineering Contradiction:
Improvememory error detection precisionVSAvoidmonitoring system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

An embedded controller is introduced as an intermediary component between the memory subsystem and the main processor. This controller专门 handles memory error monitoring, polling, and logging tasks, allowing the main processor to focus on computational tasks while achieving high-precision error detection through dedicated monitoring hardware.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The monitoring function is segmented into a separate embedded controller module with its own local memory and processing capabilities. This segmentation allows independent optimization of error detection precision without increasing overall system complexity, as the monitoring subsystem operates autonomously from the main processor.

Inventive Principle:
Principle #1Segmentation

2Speed

If high-frequency polling is implemented, then memory error monitoring timeliness is improved, but processor performance deteriorates

Engineering Contradiction:
Improveerror monitoring speedVSAvoidprocessor productivity
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The embedded controller acts as an intermediary that performs high-frequency polling of memory error status independently. It only interrupts the main processor when actual errors are detected or at scheduled log points, thereby achieving fast error monitoring without continuously burdening the processor and maintaining high processor productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements periodic polling at optimized intervals rather than continuous monitoring. The embedded controller can adjust polling frequency dynamically, performing high-frequency checks during critical periods and lower-frequency checks during normal operation, thus balancing monitoring speed with processor performance requirements.

Inventive Principle:
Principle #19Periodic action

3Loss of information

If detailed error information is recorded, then reliability analysis capability is improved, but memory usage increases

Engineering Contradiction:
Improveerror information completenessVSAvoidmemory consumption
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The embedded controller includes local memory specifically dedicated to storing error information. This local storage capability allows detailed error logs to be maintained without consuming general system memory resources. The error information is stored in a structured format optimized for reliability analysis, achieving complete error tracking with minimal impact on overall memory availability.

Inventive Principle:
Principle #3Local quality

4Measurement precision

If low-threshold interrupts are enabled, then error detection sensitivity is improved, but system interrupt frequency increases

Engineering Contradiction:
Improveerror detection sensitivityVSAvoidsystem operational efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The embedded controller serves as an intermediary that filters and manages interrupt generation. It can monitor memory errors with high sensitivity using low thresholds but intelligently manages interrupt forwarding to the main processor, batching non-critical errors and only interrupting for significant issues, thus maintaining detection sensitivity while preserving system operational efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20220350500A1Embedded controller and memory to store memory error information
Publication Date: 2022.11.03 INTEL CORP
  • US20220350500A1 patent drawing
  • US20220350500A1 patent drawing
  • US20220350500A1 patent drawing

AI summary

An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.