Embedded Controller Memory Sharing via SPI Arbitration
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Solution Overview
Problem
In computer architectures, existing techniques for sharing memory between an embedded controller and a central processing unit often result in inefficiencies, such as the need for separate memory devices and potential 'starvation' scenarios where the embedded controller is blocked from accessing memory due to high volumes of central processing unit transactions, leading to increased costs and power consumption.
Innovation Solution
The implementation of a memory control circuitry that communicates with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI) at a first clock rate and with memory over a second SPI at a higher, fixed clock rate, allowing for the identification of time intervals where no memory transactions occur and enabling the retrieval of information for the embedded controller, including software code, while continuing to operate even when memory access is blocked.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory devices are used for embedded controller and CPU chipset, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the memory resources of the embedded controller and CPU chipset into a single shared memory device. The memory control circuitry enables both processors to access the same memory space, eliminating the need for separate memory devices and reducing overall system complexity while maintaining reliable access through coordinated control mechanisms.
Solution Approach 2:
The shared memory device serves multiple functions by accommodating both the embedded controller and CPU chipset. The memory control circuitry enables the same memory resource to be universally accessed by different processors, reducing component count while ensuring reliable operation through intelligent arbitration and timing control.
2Speed
If embedded controller accesses shared memory during high CPU transaction volumes, then information retrieval speed is improved, but starvation scenarios occur
Solution Approach 1:
The memory control circuitry monitors the transaction load on the shared memory and proactively identifies optimal time intervals for the embedded controller to access memory. By performing preliminary assessment of memory availability and selecting favorable access windows before conflicts occur, the system enables fast information retrieval while preventing starvation scenarios through advance planning.
Solution Approach 2:
The system dynamically adjusts the embedded controller's memory access timing based on real-time CPU transaction volumes. The memory control circuitry continuously monitors memory utilization and adaptively selects access intervals, allowing the embedded controller to achieve high-speed access when memory is available while automatically avoiding periods of high CPU activity that would cause starvation.
3Productivity
If embedded controller uses first SPI for memory transactions, then communication efficiency is improved, but bus arbitration conflicts arise
Solution Approach 1:
The patent extracts the arbitration function from the SPI bus protocol itself and implements it within the memory control circuitry. By removing the need for complex bus arbitration mechanisms and handling access coordination internally through timing-based control, the system maintains high memory transaction efficiency while eliminating arbitration complexity.
Solution Approach 2:
The memory control circuitry acts as an intermediary between the embedded controller and the shared memory over the first SPI interface. It mediates access requests by monitoring CPU transaction patterns and intelligently scheduling embedded controller accesses, thereby maintaining high productivity while avoiding the need for complex arbitration protocols.
Data Source
AI summary
An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.