Embedded Controller Reset Sequencing for Platform Controller Hub
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Solution Overview
Problem
Information handling systems face challenges in successfully resetting platform controller hubs (PCH) after a watchdog timer (WDT) event, leading to potential system hangs due to undefined signal states on I/O pins, which prevents proper bootstrapping and restart processes.
Innovation Solution
The implementation of enhanced Serial Peripheral Interface (eSPI) master and slave devices, where the embedded controller (EC) tri-states its I/O pins and supplies specific signals like PWROK and RSMRST# to the PCH, with resistors ensuring these signals are pulled down to a logic low state, and a power controller manages voltage levels to ensure defined signal levels and proper reset sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the EC tri-states its I/O pins in response to a WDT event, then the system attempts to reset the PCH, but the I/O pins remain in an undefined logic state which prevents proper reset sequencing
Solution Approach 1:
The patent applies preliminary action by asserting the PWROK signal before reducing the operating voltage to reset the PCH. This ensures that the PCH receives a defined logic high signal in advance, preparing it for the upcoming reset condition and preventing the undefined logic state problem that would otherwise occur when the EC tri-states its I/O pins.
Solution Approach 2:
The patent uses the PWROK signal as an intermediary between the EC and PCH during the reset process. This intermediary signal mediates the transition by providing a defined logic state that bridges the gap between the EC tri-stating its pins and the PCH entering reset, thereby eliminating the harmful undefined logic state.
2Reliability
If the operating voltage is reduced to reset the PCH, then the PCH is reset, but the I/O pins remain in an undefined logic state causing system hangs
Solution Approach 1:
The patent applies preliminary action by asserting the PWROK signal to a logic high state before reducing the operating voltage. This preliminary assertion ensures that the PCH is properly prepared for reset with defined signal levels, preventing the system hangs that would otherwise occur due to undefined logic states during the voltage transition.
3Productivity
If hardware reset is initiated after WDT timeout, then the system attempts to reboot, but the reset may not propagate correctly to all system components
Solution Approach 1:
The patent uses feedback by monitoring the state of the RSMRST# signal and the operating voltage levels to determine when the PCH has successfully entered and completed its reset state. This feedback mechanism ensures that the reset has properly propagated to all necessary components before proceeding with the boot process, thereby maintaining both speed and reliability.
Solution Approach 2:
The patent applies preliminary action by asserting PWROK before voltage reduction and subsequently asserting RSMRST# after voltage restoration. This sequenced preliminary action ensures that all system components receive the reset signal in the proper order, guaranteeing complete reset propagation while maintaining efficient boot process timing.
Data Source
AI summary
Embodiments of information handling systems and methods are provided herein for resetting one or more system components in response to a watchdog timer (WDT) event. More specifically, the present disclosure provides information handling systems and methods for handling WDT events that occur within information handling systems comprising enhanced Serial Peripheral Interface (eSPI) master and slave devices.