Embedded Core Testing via Memory-Mediated Scan Chain Mimicry
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Solution Overview
Problem
Embedded cores in integrated circuits (ICs) pose a challenge for testing due to inaccessible interface pins, as scan chains may not be directly coupled to these interfaces, limiting the ability to test circuitry associated with the interface portion.
Innovation Solution
A method and system for testing an embedded core in an IC, involving writing test vectors to memory while the core is operative, mimicking scan chain input, using a write controller and memory controller to dynamically reconfigure configuration memory cells, allowing for test vector input and result retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an embedded core is manufactured as part of an FPGA, then integration and functionality are improved, but interface pins become inaccessible for testing
Solution Approach 1:
The patent introduces memory cells as an intermediary component between the embedded core and external testing equipment. These memory cells serve as a mediator that stores test vectors and makes them accessible to the core through the FPGA's configuration interface, enabling indirect testing of otherwise inaccessible interface pins
Solution Approach 2:
The system uses the FPGA's own configuration mechanism and existing memory resources to provide testing capability. Rather than requiring external specialized equipment, the FPGA leverages its built-in configuration interface and memory cells to perform self-testing of the embedded core, making the system self-sufficient for testing purposes
2Device complexity
If a scan chain is not directly coupled to the embedded core interface, then hardware overhead is reduced, but test coverage is limited
Solution Approach 1:
The patent makes the existing memory cells multi-functional by using them both for their original configuration purposes and for storing test vectors. This universal use of existing resources provides comprehensive test coverage without adding dedicated test hardware, thereby maintaining low device complexity while improving reliability
Solution Approach 2:
The system changes the functional parameter of existing memory cells from purely configuration storage to dual-purpose storage (configuration + test vectors). By altering how these resources are utilized rather than adding new hardware, the patent achieves enhanced test coverage without increasing hardware overhead
3Reliability
If traditional ATPG testing is used on embedded cores, then testing can be performed, but runtime is excessive
Solution Approach 1:
The patent performs preliminary action by pre-loading test vectors into memory cells before executing the test. This preparation phase allows the actual testing to proceed more efficiently by having test data readily available in the FPGA's memory, rather than generating and transferring test vectors during the testing process itself, thereby reducing overall testing runtime
Data Source
AI summary
A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.