Embedded Decoupling Capacitor in Through Substrate Via
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Solution Overview
Problem
The challenge in integrated circuits (ICs) is to increase decoupling capacitance without occupying significant substrate area, as conventional decoupling capacitors consume large substrate area and provide limited capacitance, while through substrate vias offer limited capacitance due to charge depletion and thick insulator layers.
Innovation Solution
Embedding a decoupling capacitor within the through substrate via by using a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric, which reduces substrate capacitance and resistance, effectively increasing capacitance per area by eliminating substrate capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional decoupling capacitors are used, then decoupling capacitance is provided, but substrate area is significantly occupied
Solution Approach 1:
The decoupling capacitor is nested within the through substrate via structure. The capacitor is formed by the conducting core, insulating sleeve, and substrate material itself, utilizing the existing via geometry to provide capacitance without requiring additional substrate area. This nested configuration allows the capacitor to be embedded within the via rather than occupying separate substrate space.
Solution Approach 2:
The invention transitions from planar capacitor designs to a three-dimensional structure by utilizing the vertical dimension of the through substrate via. The capacitance is generated along the height of the via rather than across the substrate surface, effectively using the Z-dimension to increase capacitance density without consuming additional X-Y plane area.
2Area of stationary object
If through substrate vias are used for decoupling, then substrate area is minimized, but capacitance is limited due to charge depletion and thick insulator layers
Solution Approach 1:
The invention changes the insulator layer thickness parameter by using a thin insulating sleeve instead of thick insulator layers. This parameter change directly increases the capacitance value while maintaining the through substrate via structure. Additionally, the conducting core diameter is optimized to maximize the capacitive coupling between the core and substrate.
Solution Approach 2:
The invention applies local quality by creating a specific region within the through substrate via that has enhanced capacitive properties. The insulating sleeve is positioned and dimensioned to create optimal electric field distribution, and the conducting core is designed with specific dimensions to maximize local capacitance density at the via location.
3Productivity
If transistor density is increased, then IC capabilities are extended, but voltage supplied to transistors decreases
Solution Approach 1:
The invention extracts the decoupling capacitance function from the substrate plane and embeds it within the through substrate via structure. This extraction allows the capacitance to be provided locally at the via location without interfering with the high-density transistor circuitry, ensuring stable voltage supply even as transistor density increases and voltages decrease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases capacitance per area, doubling the effective capacitance and reducing substrate resistance, outperforming conventional decoupling solutions and allowing for more compact and cost-effective IC designs.
Implementation Method 1
a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor
Implementation Method 2
a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor
Data Source
AI summary
A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias.