Embedded Decoupling Capacitors in Stacked Semiconductor Packages
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Solution Overview
Problem
Parasitic inductance in electronic systems, particularly at high clocking speeds, causes transient voltages, spurious signals, and power supply noise, degrading system performance and requiring extensive surface area for external decoupling capacitors, which are also susceptible to damage.
Innovation Solution
Semiconductor packages with discrete components embedded in the active die, such as decoupling capacitors, resistors, and inductors, are fabricated using a method involving recesses in the die and a die attach polymer to reduce inductance and eliminate the need for external capacitors, thereby improving power integrity and saving space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external decoupling capacitors are surface mounted on the system substrate, then power supply noise is filtered, but parasitic inductance increases and valuable surface area is consumed
Solution Approach 1:
The patent merges the decoupling capacitor function directly into the semiconductor package by embedding discrete capacitors within the package structure, eliminating the need for separate external capacitors. This integration reduces parasitic inductance by shortening the current path while maintaining the power supply noise filtering function.
Solution Approach 2:
The patent transitions from a two-dimensional surface mounting approach to a three-dimensional embedded approach by placing capacitors within the vertical space of the semiconductor package, utilizing the Z-dimension to reduce inductance and free up substrate surface area.
2Reliability
If external decoupling capacitors are surface mounted on the system substrate, then power supply noise is filtered, but valuable surface area on the substrate is consumed
Solution Approach 1:
The patent combines the decoupling capacitor function with the semiconductor package structure, eliminating the need for separate external capacitors that would consume valuable substrate surface area. The capacitors are embedded within the package footprint.
Solution Approach 2:
The patent nests the discrete capacitors within the semiconductor package structure, placing them in the vertical space above or within the die attach polymer layer, thereby utilizing the three-dimensional space of the package rather than requiring additional two-dimensional substrate area.
3Reliability
If external decoupling capacitors are surface mounted on the system substrate, then power supply noise is filtered, but the capacitors are susceptible to mechanical damage
Solution Approach 1:
The patent merges the decoupling capacitors into the protected interior of the semiconductor package, where they are shielded by the robust package structure and die attach polymer, eliminating their exposure to mechanical damage while maintaining the power supply noise filtering function.
Solution Approach 2:
The patent provides mechanical protection to the capacitors by embedding them within the die attach polymer and package structure before any potential mechanical damage can occur, cushioning them against shocks and stresses that would affect externally mounted components.
Data Source
AI summary
A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess, and a discrete component contained in the recess encapsulated in a die attach polymer. The stacked semiconductor package also includes interconnects electrically connecting the semiconductor dice and discrete components, and an encapsulant encapsulating the dice and the interconnects.