Embedded Multi-Die Bridge Layout for Higher Die Interconnect Density
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Solution Overview
Problem
Current microelectronic device technologies are limited in the number of chips or dies that can be interconnected due to the size constraints of silicon chips, restricting the complexity and capability of multi-die packages.
Innovation Solution
The implementation of embedded multi-die interconnect bridges (EMIBs) that are fabricated into the substrate during manufacturing, allowing for rapid communication between dies and reducing the need for space-consuming components like metal resistors, while incorporating capacitors to reduce impedance and noise, thereby enabling more efficient and flexible integration of heterogeneous dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional silicon chip interconnection methods are used, then the manufacturing process is simple, but the number of interconnectable dies is limited by silicon size constraints
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D vertical interconnection by embedding conductive bridges through the substrate thickness. Multiple dies are stacked vertically and connected via through-substrate vias, enabling interconnection of more dies without increasing the lateral footprint of individual silicon chips.
Solution Approach 2:
The patent embeds conductive bridges and intermediate connection structures within the substrate layers, nesting multiple functional elements (conductive bridges, vias, connection pads) in three-dimensional space. This allows multiple dies to be interconnected through nested vertical pathways rather than requiring large lateral areas.
2Device complexity
If more interconnections are added between dies, then the circuit complexity increases, but the silicon area required increases proportionally
Solution Approach 1:
The patent routes additional interconnection pathways through the vertical dimension using through-substrate vias and embedded conductive bridges. This allows multiple signal paths to be established between dies without increasing the lateral area occupied by routing channels on each die surface.
Solution Approach 2:
The patent divides the interconnection function into separate modular components: embedded conductive bridges, through-substrate vias, and connection pads on individual dies. This segmentation allows the interconnection infrastructure to be independently optimized and does not require proportional increases in die area for each additional connection.
3Adaptability or versatility
If space-consuming components like metal resistors are used, then the circuit functionality is achieved, but the available silicon area for other components is reduced
Solution Approach 1:
The patent extracts metal resistor components from the die surface and relocates them to the embedded bridge structure within the substrate. This extraction frees up valuable silicon area on the dies for additional functional circuitry while maintaining the necessary resistance functionality in the interconnection pathway.
Solution Approach 2:
The patent merges the function of metal resistors with the embedded conductive bridge structure. The bridge itself incorporates resistive elements as part of its construction, combining the interconnection function with the resistance function in a single integrated structure rather than requiring separate components.
4Reliability
If impedance and noise are reduced, then the signal integrity improves, but additional components like capacitors are required which increase device complexity
Solution Approach 1:
The patent combines multiple functions into the embedded bridge structure: electrical interconnection, impedance control, and noise filtering. By integrating capacitive elements directly into the bridge construction, the patent achieves signal integrity improvement without requiring separate discrete capacitor components that would increase device complexity.
Solution Approach 2:
The patent nests capacitive structures within the embedded bridge, placing filtering elements inside the interconnection pathway. This nested arrangement provides impedance control and noise reduction while utilizing the same three-dimensional space already allocated for the conductive bridge, avoiding additional lateral area requirements.
Data Source
AI summary
An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.