Embedded Die Package With Ceramic Isolation for High-Voltage Cooling
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Solution Overview
Problem
Existing embedded die packaging technologies face challenges in achieving high voltage withstand performance and thermal cooling while maintaining compact size due to the use of materials with poor electrical isolation properties, which often require thicker materials or increased creepage distances.
Innovation Solution
The integration of a ceramic substrate into the packaged electronic device, which includes a semiconductor die, an organic panel frame, and a lamination structure, along with a redistribution layer (RDL) structure, provides improved electrical isolation and thermal cooling, facilitating reduced package size and enhanced voltage withstand performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker material cross section or increased creepage distances are used to achieve high voltage withstand performance, then voltage withstand capability is improved, but package size increases
Solution Approach 1:
The patent employs a composite structure combining organic panel frame material with integrated ceramic substrate. The ceramic substrate provides superior electrical isolation properties with high dielectric strength, enabling the package to achieve high voltage withstand performance (e.g., 600V, 900V, or higher) without requiring increased creepage distances or thicker material sections. This composite approach allows compact package design while meeting high voltage requirements.
2Ease of manufacture
If materials with poor electrical isolation properties are used in panel processing, then manufacturing ease is improved, but voltage withstand performance deteriorates
Solution Approach 1:
The patent segments the package structure into distinct functional regions: an organic panel frame providing mechanical support and ease of manufacturing, and an integrated ceramic substrate providing superior electrical isolation. This segmentation allows each material to perform its optimal function - the organic material enables cost-effective panel processing while the ceramic substrate ensures high voltage withstand performance through its inherent electrical isolation properties.
3Reliability
If increased creepage distances are used to meet high voltage specifications, then functional isolation performance is improved, but device complexity increases
Solution Approach 1:
The patent fundamentally changes the material parameter (electrical isolation properties) from poor (organic-only) to excellent (ceramic-integrated). This parameter change allows the creepage distance to be minimized while still achieving the required functional isolation performance. The high dielectric strength of the ceramic substrate enables compact designs with reduced creepage distances without compromising voltage withstand capability or functional isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high voltage withstand performance with reduced creepage distances and improved thermal die cooling, suitable for compact designs using high voltage devices like GaN and SiC transistors, while also offering cost-effective panel processing benefits.
Implementation Method 1
Described examples further facilitate thermal die cooling
Implementation Method 2
a conductive via that extends through the ceramic substrate from the first side to the second side to electrically connect the first conductive layer to the second conductive layer
Implementation Method 3
a first conductive layer soldered to the first side of the embedded die structure
Data Source
AI summary
A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.