Embedded Die and Conductive Vias for High-Density Package Substrates
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Solution Overview
Problem
The challenge in IC packaging is the limited space on the package substrate, which restricts the number of IC chips that can be assembled due to the inclusion of discrete components like capacitors, and misalignment issues during die encapsulation lead to manufacturing inefficiencies and reduced yield.
Innovation Solution
A method involving a substrate core with a die having a height less than its thickness, where conductive vias extend from the die to the substrate core, and a dielectric material encapsulates the vias, ensuring proper alignment and reducing misalignment during encapsulation, allowing for efficient integration of discrete components like deep trench capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If discrete components are included on the package substrate surface, then voltage regulation circuitry is provided, but the number of IC chips that can be assembled is reduced
Solution Approach 1:
The patent embeds the die containing discrete components (capacitors, voltage regulators) within the substrate core volume rather than placing it on the surface. This transitions from two-dimensional surface mounting to three-dimensional volumetric integration, allowing discrete components to coexist with multiple IC chips on the same substrate without occupying surface assembly space.
Solution Approach 2:
The die is nested within a cavity formed in the substrate core, creating a hierarchical structure where the substrate contains the die, which in turn contains the discrete components. This nesting approach allows multiple functional elements to be integrated within the substrate assembly without interfering with surface chip placement.
2Productivity
If the package substrate size is increased to accommodate more IC chips, then the number of IC chips increases, but the discrete components cannot be integrated
Solution Approach 1:
By moving discrete components from the two-dimensional surface plane into the three-dimensional substrate volume through die embedding, the patent enables both increased chip density on the surface and integrated discrete components without requiring substrate size expansion.
3Ease of manufacture
If die encapsulation is performed without proper alignment, then manufacturing is simplified, but misalignment occurs leading to reduced yield
Solution Approach 1:
Alignment features (such as protrusions on the die and corresponding recesses in the substrate, or vice versa) are pre-formed during die or substrate fabrication before the encapsulation process. This preliminary structuring ensures automatic mechanical alignment when the die is inserted into the substrate cavity, eliminating the need for complex alignment procedures during encapsulation while guaranteeing precise positioning.
Solution Approach 2:
The alignment features act as intermediary mechanical elements that mediate between the die and substrate, providing self-aligning guidance during the encapsulation process. These features ensure that the die settles into the correct position without requiring external alignment equipment or complex positioning procedures.
Data Source
AI summary
An apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. A die is within the substrate core. The die may include a deep trench capacitor. The die has a second height between a first side of the die and a second side opposite the first side. The first height is greater than the second height. A plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. A material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. In some embodiments, a bond film is in contact with the second side of the die.