Embedded Semiconductor Die Packaging With Dual-Substrate Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging technologies struggle to meet the demands for lighter, thinner, shorter, and smaller products, particularly in the growing market for electronic devices such as smartphones and smart pads.
Innovation Solution
A semiconductor device design that embeds a semiconductor die between an extended substrate and a bottom substrate, utilizing an adhering member and conductive bumps for bonding and electrical connectivity, and encapsulating the die and bumps with a mold member.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packaging is used, then manufacturing simplicity is maintained, but the package size and weight cannot meet the demands for lighter, thinner, shorter and smaller products
Solution Approach 1:
The patent embeds the semiconductor die between two substrates (bottom substrate and extended substrate), creating a nested configuration where the die is positioned within the substrate assembly. This nesting approach reduces the overall package volume while maintaining structural integrity and electrical connectivity through multiple layers.
Solution Approach 2:
The patent transitions from conventional two-substrate stacking to a three-dimensional embedded structure where the semiconductor die is positioned between and bonded to both substrates simultaneously. This dimensional reorganization optimizes space utilization and reduces package footprint while maintaining all necessary electrical connections.
2Volume of moving object
If the semiconductor die is embedded between extended substrate and bottom substrate, then compact package size is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent forms conductive bumps on the bottom substrate before embedding the semiconductor die. This preliminary action ensures that electrical connectivity is established in advance, simplifying the subsequent embedding process and reducing manufacturing complexity despite the advanced package structure.
Solution Approach 2:
The patent introduces an adhering member as an intermediary material between the semiconductor die and substrates to facilitate bonding. This intermediary component simplifies the manufacturing process by providing a dedicated bonding interface, reducing direct complexity in die-to-substrate attachment while achieving compact packaging.
3Reliability
If conductive bumps are used for bonding substrates, then electrical connectivity is achieved, but thermal management challenges arise
Solution Approach 1:
The patent employs conductive bumps with composite material characteristics that provide both electrical conductivity and thermal conduction. These bumps serve dual functions as electrical interconnects and thermal pathways, enabling heat to be conducted away from the semiconductor die through the same structures that provide electrical connectivity, thus addressing thermal management while maintaining electrical reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the creation of compact, efficient semiconductor packages that meet the size and performance requirements of modern electronic devices, while also providing reliable electrical connectivity and thermal management.
Implementation Method 1
bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member on a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member
Implementation Method 2
bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and/or a conductive bump on the bottom substrate
Implementation Method 3
The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member
Data Source
AI summary
A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.