Embedded Die Packaging With Dielectric Edge Cushioning
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Solution Overview
Problem
Existing embedded die packaging for high voltage/high current GaN power transistors faces issues with thermal and mechanical damage during lamination and laser drilling, leading to potential cracking and delamination, which hinders qualification for harsher operating conditions such as automotive applications.
Innovation Solution
Incorporating a protective dielectric layer, such as polyimide, around the edges of the die to act as a cushion during lamination and laser drilling, and providing a patterned conductive metallization layer to protect the active regions from etch damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a laminated structure with multiple dielectric and conductive layers is used for embedded die packaging, then low parasitic inductance and compact form factor are achieved, but interlayer stresses and potential cracking/delamination occur during lamination and thermal cycling
Solution Approach 1:
A protective dielectric layer is applied to the front side of the semiconductor die before the lamination process. This preliminary protective action prevents etch damage to conductive layers and provides mechanical cushioning during lamination, thereby preventing cracking and delamination while maintaining low parasitic inductance through the embedded die structure
Solution Approach 2:
The protective dielectric layer serves as a cushioning layer that absorbs mechanical stresses during the lamination process and thermal cycling. This beforehand cushioning prevents direct stress transmission to the conductive layers and die interfaces, eliminating cracking and delamination issues while preserving the compact low-inductance structure
2Strength
If surface roughening etch is applied to the leadframe to improve adhesion, then bonding strength is enhanced, but the conductive metallization layers on the die are exposed to etch damage
Solution Approach 1:
The protective dielectric layer acts as an intermediary barrier between the etch process and the conductive metallization layers. It allows the leadframe to undergo surface roughening etch for improved adhesion while protecting the conductive layers from etch damage, thereby enabling strong bonding without harmful exposure
3Reliability
If laser drilling is used to create vias through dielectric layers for electrical connections, then low inductance interconnect is achieved, but thermal and mechanical damage may occur to contact areas and active layers
Solution Approach 1:
The protective dielectric layer is applied before laser drilling operations. This preliminary protective measure shields the contact areas and active layers from thermal and mechanical damage during laser via formation, ensuring reliable electrical interconnects without harmful effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability and durability of the packaging by mitigating physical and thermal damage, allowing the package to meet stringent qualification criteria for harsher operating conditions.
Implementation Method 1
a protective dielectric layer is provided on the front-side of the die, extending around edges of the die forming a protective region around a periphery of the die that acts a cushion to protect edges of the die from damage during lamination
Implementation Method 2
providing a patterned layer of conductive metallization on a front-side of the die, wherein the protective dielectric layer masks the patterned layer of conductive metallization to protect the patterned layer of conductive metallization from etch damage
Implementation Method 3
During subsequent laser drilling of vias through the dielectric layers, which are then filled with conductive material
Data Source
AI summary
Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.