Embedded Die Package Substrate for High-Current Interconnects
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Solution Overview
Problem
Existing semiconductor device packaging configurations struggle to accommodate sophisticated features and applications while minimizing performance impact and costs.
Innovation Solution
A semiconductor device with an embedded die is formed using a package substrate with a cavity, redistribution traces, and under-bump metallization structures, allowing for high-power applications with high current interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional packaging configurations are used, then manufacturing simplicity is maintained, but the ability to accommodate sophisticated features and applications is limited
Solution Approach 1:
The packaging configuration is segmented into distinct functional zones: a first packaging area for the semiconductor die and a second packaging area for the capacitor die. This segmentation allows each component to be independently positioned and connected, enabling sophisticated features while maintaining manageable complexity through modular design.
Solution Approach 2:
The invention transitions from planar packaging to three-dimensional stacking by positioning the capacitor die vertically above the semiconductor die. This dimensional change enables high-density interconnects and sophisticated applications without increasing the footprint, resolving the contradiction between adaptability and complexity.
2Power
If planar packaging is used, then manufacturing is simpler, but high current interconnects for high-power applications are limited
Solution Approach 1:
The interconnect structure transitions from planar to vertical three-dimensional configuration. Multiple conductive vias connect the semiconductor die to the capacitor die in the vertical dimension, enabling high current paths for high-power applications while consolidating interconnect complexity into a compact vertical architecture rather than spreading it horizontally.
Solution Approach 2:
The capacitor die is positioned within the vertical space above the semiconductor die, with conductive vias nested through the packaging substrate to connect the two dies. This nesting approach enables high current interconnects by stacking functional elements vertically, achieving high power capability without proportionally increasing overall device complexity.
3Reliability
If the semiconductor die is exposed, then access to bond pads is easier, but the die is vulnerable to damage and environmental factors
Solution Approach 1:
The semiconductor die is nested within a cavity formed in the packaging substrate, with the cavity walls providing protective enclosure. The substrate material surrounds and shields the die from environmental factors and physical damage, while the cavity design maintains accessibility to bond pads through controlled openings or via vertical interconnects.
Solution Approach 2:
The bond pad accessibility is transitioned from horizontal exposure to vertical access through the cavity structure. Bond pads remain accessible through the cavity opening or via vertical vias that penetrate the substrate, maintaining ease of operation while the three-dimensional cavity configuration provides comprehensive die protection from all lateral directions.
Data Source
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AI summary
A method of forming a semiconductor device with an embedded die is provided. The method includes forming a plurality of redistribution traces at a first major side of a package substrate. A cavity is formed in the package substrate. The plurality of redistribution traces substantially surrounding an opening of the cavity at the first major side. A semiconductor die is mounted in the cavity. A wire bond is formed between a bond pad of the semiconductor die and a wiring pad of a redistribution trace of the plurality of redistribution traces. An encapsulant encapsulates the semiconductor die and the first major side of the package substrate. A base region of the redistribution trace is exposed.