Embedded Semiconductor Die Interconnects for High-Voltage Isolation
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Solution Overview
Problem
Existing chip embedding technologies for high voltage semiconductor devices face challenges such as copper migration, oxidation of exposed metallization, chemical degradation of encapsulation material, and delamination due to high electric fields, which can lead to assembly destruction and reduced reliability.
Innovation Solution
A semiconductor device comprising a die carrier with a semiconductor die, encapsulant, insulation layer, and electrical interconnects, where the interconnects are formed through the encapsulant and insulation layer, and the encapsulant is chosen for sufficient isolation properties to handle high voltages, with interconnects fabricated using chemical plating or laser drilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If chip embedding is used for high voltage semiconductor devices, then integration density is improved, but reliability deteriorates due to copper migration and chemical degradation
Solution Approach 1:
The patent introduces an intermediate encapsulation structure that completely encloses the semiconductor die and metallization layers. This encapsulation acts as a mediator between the high voltage device and the external environment, preventing copper migration and chemical degradation while maintaining integration density.
Solution Approach 2:
The patent applies preliminary protective measures by completely enclosing the metallization layers within the encapsulation structure before the device operates. This preliminary action prevents copper migration and chemical degradation from occurring in the first place, rather than attempting to correct these issues after they arise.
2Object-affected harmful factors
If encapsulation material is used to cover the die, then protection is improved, but chemical degradation occurs due to interaction with high voltage electric fields
Solution Approach 1:
The patent employs composite material structures, combining the semiconductor die with an encapsulation material that is specifically selected to be resistant to chemical degradation from high voltage electric fields. This composite structure provides both protection and stability in high voltage environments.
3Ease of operation
If vias are created to connect to outer layers, then electrical connection is improved, but crack formation increases at the via-to-die metallization interface
Solution Approach 1:
The patent performs preliminary actions by establishing robust via structures and reinforcement features before the device undergoes thermal cycling or mechanical stress. This preliminary strengthening of the via-to-die metallization interface prevents crack formation during subsequent operation.
4Stability of the object's composition
If leadframe cavities are used to prevent delamination, then structural stability is improved, but manufacturing complexity increases due to dedicated cavity requirements
Solution Approach 1:
The patent creates a universal encapsulation structure that serves multiple functions simultaneously: it provides structural stability to prevent delamination, protects against environmental factors, and accommodates the semiconductor die. This single multi-functional structure eliminates the need for separate leadframe cavities, reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and robustness of high voltage semiconductor devices by preventing copper migration and chemical degradation, ensuring reliable electrical connections and improved thermal conductivity.
Implementation Method 1
an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier
Implementation Method 2
one or more electrical interconnects each being connected with one of the contact pads of the semiconductor die and extending through the encapsulant
Data Source
AI summary
A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.