Embedded Semiconductor Die Packaging for High-Voltage Reliability
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Solution Overview
Problem
High-voltage semiconductor devices face challenges such as copper migration, oxidation of exposed copper metallization, and chemical degradation of encapsulation materials due to high electric fields, leading to potential destruction of the assembly and reliability issues during the embedding process.
Innovation Solution
A semiconductor device comprising a die carrier with a semiconductor die, an encapsulant covering the die and die carrier, and an insulation layer, along with electrical interconnects that extend through the encapsulant and insulation layer, fabricated using methods like electroplating or laser drilling to enhance reliability and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip embedding is used for high voltage semiconductor devices, then integration is achieved, but copper migration and chemical degradation occur due to high electric fields
Solution Approach 1:
The patent introduces an intermediate encapsulation structure that isolates the high-voltage semiconductor die from the embedding environment. The encapsulant material acts as a mediator between the die and the surrounding embedding material, preventing direct interaction that would cause copper migration and chemical degradation while still allowing the device to be embedded in the circuit board.
Solution Approach 2:
The patent creates an inert protective environment around the semiconductor die through the encapsulation structure. This encapsulated space provides an inert atmosphere that protects the exposed copper metallization from oxidation and prevents the die from interacting with harmful substances in the embedding material, thereby maintaining reliability in high-voltage conditions.
2Ease of operation
If exposed copper metallization is present on the die, then electrical connection is enabled, but oxidation occurs requiring special treatment
Solution Approach 1:
The encapsulation structure creates an inert atmosphere that envelops the exposed copper metallization on the die. This protective environment prevents oxygen from reaching the copper surfaces, thereby preventing oxidation while maintaining the electrical connection functionality of the exposed metallization.
3Ease of operation
If vias are used to connect outer layers to the die, then electrical connection is achieved, but cracks occur at the via-to-die metallization interface
Solution Approach 1:
The encapsulation structure provides beforehand cushioning by creating a compliant intermediate layer between the rigid via structures and the die metallization. This encapsulant material absorbs mechanical stresses and prevents crack propagation at the via-to-die interface, maintaining interface strength while allowing electrical connection.
4Object-affected harmful factors
If encapsulation material is used to cover the die, then protection is provided, but chemical degradation occurs due to interaction with high voltage electric fields
Solution Approach 1:
The patent employs composite encapsulation materials that combine multiple properties: electrical insulation, chemical inertness to high-voltage fields, and mechanical compliance. This composite structure provides protection against environmental factors while resisting chemical degradation from high-voltage electric fields, maintaining long-term material stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses the reliability and robustness concerns by preventing delamination and chemical degradation, ensuring high reliability and robustness of high-voltage semiconductor devices.
Implementation Method 1
an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier
Implementation Method 2
an insulation layer covering the encapsulant
Implementation Method 3
one or more electrical interconnects each being connected with one of the contact pads of the semiconductor die and extending through the encapsulant
Implementation Method 4
fabricated using methods like electroplating or laser drilling
Implementation Method 5
fabricated using methods like electroplating or laser drilling
Data Source
AI summary
A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.