Embedded Local Interconnect Packaging for High-Bandwidth Die Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and reliable communication bandwidth between integrated circuit dies due to warpage mismatch and coefficient of thermal expansion (CTE) mismatch between package structures, particularly in Package-on-Package (PoP) technology, where the need for interposers complicates packaging and reduces reliability.
Innovation Solution
The implementation of a solder-free embedded local interconnect component within a redistribution structure, which provides electrical connection between integrated circuit dies and reduces the need for interposers by increasing communication bandwidth, while maintaining low contact resistance and high reliability through copper-to-copper bonding or hybrid bonding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Package-on-Package (PoP) technology is used to achieve high integration density, then component density and functionality are enhanced, but warpage mismatch and CTE mismatch occur between package structures
Solution Approach 1:
The patent changes the material parameters of the interconnect component by using a substrate with CTE matched to the semiconductor die (e.g., silicon substrate for silicon die). This parameter matching resolves the CTE mismatch issue in PoP structures, preventing warpage and improving reliability while maintaining high integration density.
Solution Approach 2:
The patent introduces an interconnect component as an intermediary element between the semiconductor die and the package substrate. This intermediary contains TSVs that provide electrical connection and mechanical support, acting as a buffer that absorbs stress and reduces warpage mismatch between the die and package substrate.
2Reliability
If interposers are used in PoP technology to provide electrical connection, then communication bandwidth is enabled, but device complexity increases and reliability decreases
Solution Approach 1:
The patent extracts the essential function of the interposer (providing electrical connection via TSVs) and integrates it directly into the semiconductor die structure. By forming TSVs directly in the die substrate rather than using a separate interposer component, the patent reduces packaging complexity while maintaining communication bandwidth and improving reliability.
Solution Approach 2:
The patent merges the interposer function with the semiconductor die by integrating TSV formation directly into the die fabrication process. This consolidation eliminates the need for separate interposer components and reduces the number of assembly steps, thereby reducing device complexity while maintaining electrical connection capabilities.
3Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses the integration density challenge by transitioning from planar integration to three-dimensional integration using vertical TSV structures. This dimensional change allows more components to be integrated without continuously reducing minimum feature size, as the TSVs provide vertical interconnect pathways that multiply the effective connection capacity in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances communication bandwidth between integrated circuit dies, reduces warpage mismatch, and increases component and board-level reliability by eliminating the need for interposers and improving thermal expansion compatibility, thus enabling more efficient and compact semiconductor packaging.
Implementation Method 1
maintaining low contact resistance and high reliability through copper-to-copper bonding or hybrid bonding techniques
Implementation Method 2
maintaining low contact resistance and high reliability through copper-to-copper bonding or hybrid bonding techniques
Implementation Method 3
forming a dielectric layer over the interconnect component
Implementation Method 4
provides electrical connection between integrated circuit dies and increases communication bandwidth
Implementation Method 5
The core substrate may be bonded to a second side of the redistribution structure using a set of conductive connectors
Data Source
AI summary
In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.