Embedded-Die Through-Via Interposer for Low-Warpage PoP Packaging
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Solution Overview
Problem
Existing technologies face challenges in minimizing warpage and reducing z-height in package-on-package arrangements, which are crucial for reducing the footprint of electronic devices as they become smaller.
Innovation Solution
The use of a through-via interposer with an embedded die package, which includes conductive vias that electrically connect the front side and back side of the package, allowing for back side package interconnects and enabling the stacking of additional packages or dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If package-on-package arrangements are used to reduce footprint, then device area is reduced, but warpage increases
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between stacked packages. This interposer acts as a mediator that provides a large-area support structure and heat dissipation path, thereby reducing warpage in the compact package-on-package arrangement while enabling the reduced footprint design.
2Area of moving object
If package-on-package arrangements are used to reduce footprint, then device area is reduced, but z-height increases
Solution Approach 1:
The patent utilizes the z-dimension (vertical stacking) to achieve high integration density while the interposer provides lateral heat dissipation and mechanical support. This dimensional approach allows compact footprint while managing the z-height through proper thermal and structural design of the interposer substrate.
3Stability of the object's composition
If through-via interposer with embedded die is used, then warpage is minimized and z-height is reduced, but manufacturing complexity increases
Solution Approach 1:
The die is embedded into the interposer substrate during the substrate fabrication process itself, before the final package assembly. This preliminary action of embedding the die during manufacturing allows for simplified subsequent assembly steps and reduces overall manufacturing complexity despite the advanced structure.
Solution Approach 2:
The patent merges the die embedding process with the interposer fabrication process. By combining these two operations into a unified manufacturing flow, the patent reduces the number of separate manufacturing steps and lowers overall complexity while achieving the warpage minimization benefits of the embedded structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively minimizes warpage and reduces z-height, enabling more compact package-on-package arrangements while maintaining reliable electrical connectivity.
Implementation Method 1
an interposer having one or more conductive through-vias
Data Source
AI summary
Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.