Embedded Die Substrate on Interposer for Yield and Dimensional Control
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Solution Overview
Problem
Conventional processes for manufacturing embedded die substrates in microelectronic devices are prone to inconsistencies and yield losses, especially with increasing bump pitch scaling and higher die counts, leading to variations in substrate dimensions and integration complications.
Innovation Solution
The implementation of a microelectronic device with an embedded die substrate on an interposer, featuring a single transverse routing layer and vertical through contacts, where the interposer handles redistribution functionality, simplifying manufacturing and improving dimensional control by eliminating multiple transverse routing layers from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple transverse routing layers are defined within the substrate using conventional buildup processes, then routing functionality is provided, but variations in bump height (BTV) and manufacturing inconsistencies occur
Solution Approach 1:
The patent extracts the redistribution routing functionality from the substrate and relocates it to a separate interposer component. The substrate is simplified to contain only the embedded die and essential vertical through-silicon vias (TSVs), while the interposer provides all transverse routing layers and redistribution functions. This separation eliminates the complexity of forming multiple routing layers within the substrate itself, thereby reducing bump height variations and improving manufacturing precision.
Solution Approach 2:
The patent segments the microelectronic device into distinct functional components: a simplified substrate containing the embedded die and vertical interconnects, and a separate interposer containing all transverse routing layers and redistribution logic. This segmentation allows each component to be optimized independently - the substrate for precise die embedding and the interposer for flexible routing - thereby resolving the contradiction between manufacturing simplicity and precision.
2Adaptability or versatility
If multiple embedded die are integrated within the substrate, then functionality is enhanced, but dimensional control and integration consistency become more difficult
Solution Approach 1:
The patent extracts the routing and redistribution functionality from the substrate, leaving the substrate to focus solely on precise die embedding and vertical interconnection. The interposer then handles all lateral routing and dimensional adjustments, allowing multiple embedded die to be integrated with consistent dimensional control regardless of die count or thickness variations.
3Productivity
If bump pitch scaling is reduced to increase die count, then device density is improved, but substrate process variations become more problematic
Solution Approach 1:
The patent extracts all transverse routing functionality from the substrate to a separate interposer. This allows the substrate to be manufactured with simplified processes that are less sensitive to pitch scaling, while the interposer provides the high-density routing layer at the scaled bump pitch, thereby decoupling substrate manufacturing precision requirements from bump pitch scaling.
4Adaptability or versatility
If lateral dimensions of the substrate are increased to accommodate higher die counts, then device capacity is improved, but manufacturing complexity and process variations increase
Solution Approach 1:
The patent extracts the complex transverse routing network from the substrate and places it in the interposer. This allows the substrate to maintain simpler manufacturing processes even as lateral dimensions and die counts increase, while the interposer accommodates the increased complexity of routing and redistribution for high-capacity devices.
Data Source
AI summary
A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.