Embedded Die Package Laser Routing Alignment
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Solution Overview
Problem
Current chip packaging technologies face challenges with alignment issues and reliability due to manufacturing tolerances and pick-and-place robot limitations, leading to increased unit costs and reduced yields, especially for complex IC chips with high contact densities.
Innovation Solution
The development of an embedded die package with individually drawn routing lines and pillars that are aligned with I/O contact pads using laser writing, allowing for precise alignment and improved contact reliability, even with misaligned or rotated dies, and the use of a method involving a grid of sockets surrounded by a polymer frame for chip packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional pick-and-place robots are used for chip assembly, then manufacturing cost is reduced, but alignment precision and contact reliability deteriorate due to robot limitations and manufacturing tolerances
Solution Approach 1:
The patent applies preliminary action by pre-forming sockets with integrated alignment features and registration marks before chip placement. The socket structure includes built-in mechanical guides and alignment pins that automatically position the chip during assembly, eliminating the need for high-precision robotic positioning. This preliminary preparation of the mounting structure enables conventional robots to achieve precise alignment without requiring advanced positioning systems.
Solution Approach 2:
The patent introduces an intermediary component - the socket with integrated alignment features - that mediates between the chip and the mounting substrate. This socket acts as a buffer that absorbs positioning tolerances and provides mechanical guidance, allowing conventional pick-and-place robots to achieve precise alignment. The socket's alignment features serve as an intermediate reference system that translates rough robot positioning into precise chip placement.
2Reliability
If manufacturing tolerances are relaxed to reduce costs, then unit price decreases, but alignment accuracy and contact reliability worsen
Solution Approach 1:
The socket is pre-formed with integrated alignment features including registration marks and mechanical guides that establish precise positioning references before chip assembly. This preliminary preparation enables the system to compensate for variations in chip positioning and routing line placement, maintaining contact reliability even when manufacturing tolerances are relaxed in subsequent processing steps.
Solution Approach 2:
The patent employs parameter changes by using laser writing to create routing lines with variable positioning that adapts to the actual chip location. The system adjusts the routing line parameters (position, orientation) based on the chip's actual placement within the socket, compensating for alignment variations and ensuring reliable contact between routing lines and contact pads despite relaxed manufacturing tolerances.
3Reliability
If laser writing is used to individually draw routing lines for precise alignment, then contact reliability improves, but manufacturing complexity and process time increase
Solution Approach 1:
The socket structure is pre-formed with integrated alignment features and registration marks that establish a reference framework before laser writing. This preliminary preparation enables the laser writing process to quickly and accurately draw routing lines by referencing pre-established markers, reducing the time required for precise alignment compared to creating all alignment features during the laser writing process itself.
Solution Approach 2:
The patent uses a standardized socket design with repeating alignment features and registration marks that can be copied across multiple chips. Once the laser writing process is optimized for one chip type, the same routing line patterns and alignment procedures can be replicated for identical chip types, significantly improving manufacturing speed through process standardization and reuse.
4Measurement precision
If alignment features are integrated into the socket structure, then alignment precision improves, but socket fabrication complexity increases
Solution Approach 1:
The patent merges multiple functions into the socket structure by integrating alignment features, mechanical guides, and registration marks directly into the socket body during a single fabrication process. This consolidation eliminates the need for separate alignment components or post-assembly alignment procedures, simplifying the overall manufacturing process despite the increased complexity of the socket structure itself.
Solution Approach 2:
The socket is designed with universal alignment features that serve multiple purposes: providing mechanical guidance during chip placement, establishing reference marks for laser writing, and ensuring proper orientation. This multi-functionality reduces the need for separate specialized components and simplifies the manufacturing process by using a single integrated structure for multiple alignment-related functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of chip packaging by ensuring accurate alignment and contact between routing lines and termination pillars, enabling the packaging of complex IC chips with high contact densities while reducing unit costs.
Implementation Method 1
selective exposure to light of an appropriate wavelength, typically ultraviolet, either by selective exposure to a lamp through a stencil or by writing the pattern using a laser scribe
Implementation Method 2
This technology of electroplating into a pattern developed into a photo-resist is known as 'pattern plating'
Implementation Method 3
a seed layer is first deposited. Then a layer of photo-resist is deposited thereover
Data Source
AI summary
An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.