Embedded Die Interconnection via Micro Bumps
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Solution Overview
Problem
Integrated circuit devices with embedded die face challenges in achieving high-density, low-latency interconnections without using costly and complex through-silicon vias (TSVs), which increase latency and fabrication complexity.
Innovation Solution
Directly connecting mother and daughter die through micro bumps embedded in a substrate, forming a high-density interconnection path without TSVs, allowing for alignment and overlap to reduce footprint and simplify the chip attach process, while using surface routing and underfill to enhance mechanical and thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-silicon vias (TSVs) are used for interconnection, then interconnection density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent extracts the complex TSV fabrication process entirely and replaces it with a simplified micro bump interconnection method. Daughter dies are embedded in the substrate and connected to mother dies through micro bumps, eliminating the need for through-silicon via formation while maintaining high interconnection density.
Solution Approach 2:
The patent uses micro bumps instead of expensive TSV structures. Micro bumps are simpler, cheaper to fabricate, and can be formed using standard bumping processes rather than the complex TSV formation requiring deep etching, filling, and planarization.
2Quantity of substance
If through-silicon vias (TSVs) are used for interconnection, then interconnection density is improved, but latency increases
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional embedded die architecture. Daughter dies are embedded within the substrate, creating vertical stacking that reduces signal path length and latency while maintaining high interconnection density through spatial optimization.
3Area of stationary object
If daughter die are embedded in substrate, then footprint is reduced, but alignment precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment and bonding of daughter dies to the substrate before final assembly. This preliminary action allows for precise positioning and bonding under controlled conditions, reducing the risk of misalignment in subsequent steps and enabling compact three-dimensional packaging.
Data Source
AI summary
Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.