Embedded Die Package Multichip Module Parasitic Inductance Reduction
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Solution Overview
Problem
Current semiconductor packaging designs rely on wirebonding, which increases parasitic inductance and can lead to noise loops and packaging material failure, especially when high power and high current devices are used together.
Innovation Solution
An embedded die package design that incorporates multiple dies within a single package, using vias and redistribution layers to minimize noise loops and parasitic inductance, with a build-up material to increase spacing and mitigate arcing, and a post for connecting RDL layers to reduce manufacturing stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonding is used to provide electrical connections, then electrical connectivity between dies and package is achieved, but parasitic inductance increases and noise loops are formed
Solution Approach 1:
The patent removes the wirebonding element from the package structure entirely, replacing it with direct die-to-package mounting and conductive patterns formed on the package substrate. This extraction eliminates the source of parasitic inductance and noise loops while maintaining electrical connectivity through alternative pathways.
Solution Approach 2:
The package substrate acts as an intermediary, providing conductive patterns that route signals between dies and external connections. This mediator eliminates the need for wirebonds by creating direct conductive pathways through the substrate, reducing parasitic effects while maintaining connectivity.
2Power
If high power and high current devices are used together, then power processing capability is improved, but packaging material failure risk increases due to noise loops
Solution Approach 1:
By removing wirebonds from the structure, the patent eliminates the noise loops that cause packaging material failure. This allows high power and high current devices to be used together without the reliability penalty associated with traditional wirebonded connections.
3Object-generated harmful factors
If vias and redistribution layers are used to minimize noise loops, then parasitic inductance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the via and redistribution layer functions into an integrated substrate structure. The conductive patterns are formed directly on the package substrate during manufacturing, merging what would otherwise be separate complex components into a unified structure that reduces both parasitic inductance and overall complexity.
Solution Approach 2:
The patent transitions from three-dimensional wirebond connections to two-dimensional conductive patterns on the substrate plane. This dimensional change simplifies the structure by eliminating vertical wirebond loops while maintaining electrical connectivity through planar conductive paths.
4Object-affected harmful factors
If build-up material is used to increase spacing between high voltage die and RDL, then arcing is mitigated, but manufacturing steps increase
Solution Approach 1:
The build-up material is applied during the manufacturing process before final assembly, preliminarily establishing the required spacing between high voltage dies and redistribution layers. This preliminary action prevents arcing issues before they can occur and integrates the spacing requirement into the manufacturing flow rather than adding post-assembly complexity.
Data Source
AI summary
An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.