Embedded-Die Patch Layout for Low Bump Top Variation
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Solution Overview
Problem
Conventional processes for manufacturing microelectronic devices with embedded dies suffer from inconsistencies and yield losses due to variations in solder bump height and die thickness, which become more problematic as bump pitch scales down, leading to increased Bump Top Variation (BTV) and integration complications.
Innovation Solution
A novel microelectronic device patch design that accommodates embedded dies of varying thickness with a single transverse routing layer, using a process that includes forming patterned metallization layers, dielectric encapsulation, and vertical contacts to reduce BTV to less than 10 microns, facilitating improved dimensional control and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional buildup processes with multiple transverse routing layers are used, then electrical connectivity is achieved, but Bump Top Variation (BTV) increases and manufacturing precision deteriorates
Solution Approach 1:
The patent extracts and eliminates the multiple transverse routing layers from the substrate structure, retaining only a single transverse routing layer. This extraction of unnecessary complexity directly reduces Bump Top Variation while maintaining essential electrical connectivity functions through alternative routing approaches.
Solution Approach 2:
The patent segments the routing function by separating transverse routing from vertical interconnect functions. Vertical connections are achieved through vias and conductive structures that penetrate through the substrate, while the single transverse routing layer handles lateral signal distribution, dividing the complex multi-layer routing problem into simpler functional segments.
2Adaptability or versatility
If multiple dies of different thicknesses are embedded in the substrate, then heterogeneous integration is achieved, but variations in die thickness cause inconsistencies and yield losses
Solution Approach 1:
The patent applies local quality by providing individual compensation structures for each embedded die based on its specific thickness characteristics. Rather than requiring all dies to be uniform thickness, the substrate structure is locally adapted to accommodate varying die thicknesses, with routing layers and interconnect structures adjusted in the regions surrounding each die to maintain consistent bump heights and electrical performance.
Solution Approach 2:
The patent changes the physical parameters of the substrate structure, including routing layer thickness, via dimensions, and interconnect geometry, to compensate for variations in embedded die thickness. These parameter adjustments allow the substrate to accommodate heterogeneous dies while maintaining consistent manufacturing outcomes and yield.
3Quantity of substance
If bump pitch is scaled down, then device density is improved, but Bump Top Variation becomes more problematic and manufacturing precision deteriorates
Solution Approach 1:
By extracting and eliminating multiple transverse routing layers, the patent reduces the cumulative thickness variations that contribute to Bump Top Variation. This simplification is particularly beneficial for fine-pitch applications where even small variations can cause manufacturing defects, enabling reliable production at higher device densities.
Data Source
AI summary
Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.