Embedded-Die Patch Layout for Mixed Die Thickness and Low BTV
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Solution Overview
Problem
Conventional processes for manufacturing microelectronic devices with embedded dies suffer from inconsistencies and yield losses due to variations in solder bump height and die thickness, which become more problematic as bump pitch scales down, leading to increased bump top variation (BTV) and integration complications.
Innovation Solution
The development of a microelectronic device patch with embedded dies of varying thickness, utilizing a process that includes a single transverse routing layer and advanced dielectric and conductive structures to reduce BTV, allowing for improved dimensional control and higher heterogeneous integration while maintaining high yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional buildup processes with multiple transverse routing layers are used, then substrates can be formed with embedded die, but variations in solder bump height and BTV increase
Solution Approach 1:
The patent reduces the number of transverse routing layers from multiple to a single layer, segmenting the substrate structure to simplify the buildup process. This segmentation eliminates unnecessary intermediate layers that contribute to BTV, while still providing required routing functionality through the single optimized transverse routing layer.
Solution Approach 2:
The patent changes the structural parameters of the substrate by reducing the number of routing layers and optimizing the thickness of remaining layers. This parameter change directly reduces the cumulative variation in solder bump height and BTV, improving manufacturing precision while maintaining ease of manufacture through simplified processes.
2Adaptability or versatility
If multiple die of different thicknesses are embedded in the substrate, then functional integration is achieved, but BTV increases significantly
Solution Approach 1:
The patent applies local quality by allowing different die thicknesses at different locations within the substrate while maintaining overall BTV control. Each embedded die can have locally optimized thickness for its specific function, and the single transverse routing layer structure compensates for thickness variations to maintain uniform bump topology across the entire substrate.
Solution Approach 2:
The patent changes the structural parameters by implementing a single transverse routing layer with optimized dielectric thicknesses. This parameter change allows the substrate to accommodate dies of varying thicknesses (heterogeneous integration) while maintaining consistent bump height through the simplified layer structure that reduces cumulative variation.
3Productivity
If bump pitch is scaled down to increase density, then device integration is improved, but BTV becomes more problematic
Solution Approach 1:
The patent segments the routing structure into a single transverse routing layer, reducing the number of interfaces and lamination steps. This segmentation minimizes the accumulation of manufacturing variations that would otherwise be magnified at smaller bump pitches, enabling higher integration density with controlled BTV.
Solution Approach 2:
The patent changes the substrate layer parameters by reducing the number of routing layers and optimizing dielectric thicknesses. This parameter change reduces the cumulative effect of manufacturing variations, enabling successful implementation of smaller bump pitches with adequate BTV control for high-density integration.
Data Source
AI summary
Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.