Embedded Semiconductor Die Packaging for Thin Thermal Interconnects
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in creating lightweight, thin, short, and small packages that meet the growing demands of electronic devices like smartphones and smart pads, as they struggle to efficiently integrate semiconductor dies between substrates while ensuring electrical connectivity and thermal management.
Innovation Solution
A semiconductor device design that embeds a semiconductor die between an extended substrate and a bottom substrate, using conductive bumps and an adhering member for bonding, and encapsulating with a mold member, allowing for various coupling methods such as ball-to-ball, ball-to-post, post-to-ball, and post-to-post connections to achieve efficient electrical and thermal integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packaging methods are used, then electrical connectivity can be achieved, but the package size and weight cannot be reduced sufficiently for modern electronic devices
Solution Approach 1:
The patent transitions from planar substrate connections to three-dimensional vertical stacking, where semiconductor dies are bonded between substrates in the thickness direction. This dimensional change enables compact packaging while maintaining electrical connectivity through vertical interconnections rather than lateral routing.
Solution Approach 2:
The patent embeds semiconductor dies between substrates, creating a nested structure where the die is positioned within the space between the extended substrate and bottom substrate. This nesting approach maximizes space utilization and reduces overall package volume while preserving functional connectivity.
2Length of stationary object
If substrate thickness is reduced to achieve thinner packages, then portability improves, but thermal management becomes more difficult
Solution Approach 1:
The patent introduces an adhering member as an intermediary layer between the semiconductor die and substrates. This adhering member serves dual functions: providing mechanical bonding while also acting as a thermal interface material to facilitate heat transfer from the die to the substrates, thus managing thermal loads in thin packages.
Solution Approach 2:
The patent employs composite material structures where substrates and adhering members are combined to achieve both mechanical support and thermal management functions. The composite construction allows optimization of thermal pathways while maintaining the reduced thickness required for portable devices.
3Reliability
If complex bonding methods are used to ensure reliable electrical connectivity, then connection reliability improves, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent uses pre-formed conductive bumps on substrates that are prepared in advance. These bumps are positioned and configured before the bonding process, simplifying the subsequent assembly steps. The preliminary preparation of connection structures reduces manufacturing complexity while ensuring reliable electrical connectivity through the established bump configurations.
Solution Approach 2:
The bonding process utilizes self-aligning features where the conductive bumps and adhesive layers automatically position themselves during assembly. This self-service mechanism reduces the need for complex alignment procedures and manual intervention, thereby simplifying manufacturing while maintaining connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the creation of compact, efficient semiconductor packages that meet the size and performance requirements of modern electronic devices by ensuring reliable electrical connectivity and thermal management, while allowing for flexible manufacturing processes.
Implementation Method 1
bonding an extended substrate to the semiconductor die and to the bottom substrate utilizing the adhering member
Implementation Method 2
conductive bumps and an adhering member for bonding, and encapsulating with a mold member, allowing for various coupling methods such as ball-to-ball, ball-to-post, post-to-ball, and post-to-post connections to achieve efficient electrical and thermal integration
Implementation Method 3
achieve efficient electrical and thermal integration
Data Source
AI summary
A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.