Embedded Semiconductor Die in Penetrable Encapsulant Between TSV Interposers
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Solution Overview
Problem
There is a need for an efficient die stacking structure with a fine pitch vertical interconnect in semiconductor devices to meet increasing signal processing requirements and enhance input/output (I/O) count.
Innovation Solution
The method involves providing substrates with conductive vias and embedding a semiconductor die between them, forming an interconnect structure, and using an encapsulant between the substrates to create a thin structure with efficient z-direction vertical interconnects, allowing for fine pitch and high I/O count connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semiconductor die is mounted over a temporary support carrier with an adhesive layer and encapsulated, then environmental protection is achieved, but the device thickness increases and vertical interconnect efficiency decreases
Solution Approach 1:
The patent removes the temporary support carrier and adhesive layer from the packaging structure, extracting unnecessary components that increase thickness. The semiconductor die is directly encapsulated in the molding compound, eliminating the carrier assembly and reducing overall device thickness while maintaining environmental protection.
Solution Approach 2:
The patent transitions from a planar mounting structure to a three-dimensional embedded structure. The semiconductor die is embedded within the molding compound with vertical interconnect structures extending through the encapsulant, enabling efficient z-direction connections and reducing the need for thick adhesive layers and carrier structures.
2Ease of manufacture
If traditional WLP mounting structures are used with carrier and adhesive layers, then ease of manufacture is maintained, but vertical interconnect pitch increases and I/O count decreases
Solution Approach 1:
The patent segments the manufacturing process into die attachment, encapsulation, and interconnect formation as separate sequential steps. This allows each process to be optimized independently, achieving fine pitch vertical interconnects through specialized equipment while maintaining overall manufacturing simplicity.
Solution Approach 2:
The molding compound serves as an intermediary material that enables both fine pitch vertical interconnects and ease of manufacture. The encapsulant provides a matrix through which conductive vias can be formed with high precision, while the overall encapsulation process remains simple and compatible with existing WLP manufacturing equipment.
3Quantity of substance
If multiple substrate layers are stacked with conductive vias, then I/O count increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the substrate, encapsulant, and interconnect structures into a single integrated molding compound matrix. Multiple conductive vias are formed through the encapsulant to connect stacked semiconductor dies, combining what would otherwise be separate substrate and interconnect components into one unified structure, thereby increasing I/O count while reducing overall device complexity.
Data Source
AI summary
A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.