Embedded DRAM Codeword Storage for Low-Capacitance Memory Arrays
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Solution Overview
Problem
Embedded dynamic random access memory (DRAM) designs face challenges due to low capacitance and large area requirements, leading to reduced signal output and increased semiconductor area, as they rely on non-optimized planar capacitive structures rather than the optimized capacitive cells used in dedicated DRAM devices.
Innovation Solution
The use of information coding techniques, specifically mapping data words into storage format words using Hadamard matrices, allowing for collective optimization of bit characteristics during storage and retrieval, which reduces the number of storage cells needed and improves signal integrity by interpreting charge levels through maximal likelihood decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If planar capacitive structures are used for embedded memory, then the memory can be integrated into custom semiconductor logic devices, but the capacitance is low and the area is large
Solution Approach 1:
The patent changes the fundamental parameter of how data is stored - transitioning from storing individual bits in separate capacitive cells to storing encoded codewords across multiple cells. This parameter change allows the system to achieve the required storage capacity with fewer, smaller cells, directly reducing the semiconductor area while maintaining integration capability into custom logic devices.
Solution Approach 2:
The patent segments the storage approach by dividing data into codewords that are distributed across multiple storage cells. Instead of dedicating one cell per bit, the system segments information into codeword units that can be stored collectively, improving space utilization and reducing the total area required for embedded memory arrays.
2Adaptability or versatility
If planar capacitive structures with low capacitance are used, then integration is achieved, but the signal output is reduced
Solution Approach 1:
The patent merges multiple bit signals into codeword-level operations. By combining several bits into codewords and performing storage and retrieval operations at the codeword level, the system accumulates signal strength across multiple cells, compensating for the low capacitance of individual planar structures and restoring adequate signal output levels.
Solution Approach 2:
The patent changes the operational parameter from bit-level to codeword-level processing. This parameter change allows the system to leverage the collective capacitance of multiple cells for each codeword, effectively increasing the signal output despite using low-capacitance planar structures, while maintaining compatibility with custom logic device integration.
3Reliability
If larger storage elements are used to compensate for low capacitance, then signal output is improved, but the semiconductor area increases significantly
Solution Approach 1:
The patent merges the storage function across multiple smaller cells rather than relying on a single large cell. By distributing codeword storage across multiple planar capacitive cells and performing collective readout, the system achieves adequate signal output through signal accumulation without requiring individual cells to be larger, thus avoiding the area penalty.
Solution Approach 2:
The patent introduces a new dimension to the storage problem by operating at the codeword level rather than the bit level. This dimensional change in the data organization hierarchy allows the system to exploit spatial distribution across multiple cells to achieve signal strength, replacing the need for larger individual cell capacitance with a multi-cell collaborative approach that conserves area.
Data Source
AI summary
A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words.