Embedded DRAM Compression Circuitry for Area and Power Reduction
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Solution Overview
Problem
Modern system on a chip (SoC) technologies face challenges in balancing the increase in capacity and performance of embedded dynamic random-access memory (DRAM) with higher power and area requirements, necessitating innovative design approaches to improve performance without significant penalties in power and area.
Innovation Solution
The integration of embedded DRAM memory cells using thin-film transistors as selector transistors, with memory arrays fabricated in higher metal layers and peripheral circuits located below, allowing for reduced footprint area and closer proximity for improved latency and power efficiency, along with the inclusion of compression/decompression and homomorphic compute circuits to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded DRAM capacity and performance are increased, then memory performance is improved, but power consumption and area requirements increase
Solution Approach 1:
The patent implements compression circuits and decompression circuits within the memory array structure itself, nesting these functional units inside the memory cells. This allows compression/decompression operations to be performed in-place without requiring separate external circuitry, thereby improving memory performance while avoiding the area and power penalties of external compression devices
Solution Approach 2:
The patent combines multiple functions (storage, compression, decompression) into a single integrated memory structure. By merging the compression circuit, decompression circuit, and memory array into one unified system, the patent achieves improved memory performance while reducing the overall area and power consumption compared to separate implementations
2Productivity
If embedded DRAM capacity and performance are increased, then memory performance is improved, but area requirements increase
Solution Approach 1:
The compression and decompression circuits are nested within the memory array structure, utilizing the same physical space for multiple functions. This nesting approach enables enhanced memory performance without proportionally increasing the chip area, as the compression/decompression functionality is embedded within the existing memory cell layout
Solution Approach 2:
The patent utilizes vertical stacking of circuit layers to implement compression and decompression circuits in three-dimensional space within the memory structure. By transitioning from a two-dimensional layout to a multi-layer vertical architecture, the patent achieves improved memory performance while maintaining a compact footprint area
3Area of stationary object
If memory arrays are fabricated in higher metal layers with peripheral circuits below, then footprint area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements a three-dimensional vertical stacking architecture where memory arrays are fabricated in higher metal layers and peripheral circuits are placed in lower layers. This vertical dimensionality change reduces the horizontal footprint area while managing manufacturing complexity through systematic layer assignment and interconnect routing strategies
Data Source
AI summary
Method and apparatus to implement an integrated circuit (IC) device to perform compression/decompression operations. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compression/decompression circuitry to perform compression operations on data to be written to the memory array and decompression operations on data read from the memory array. The memory array and the compression/decompression circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compression/decompression circuitry in a same x-y plane.