Embedded DRAM Refresh Control Using Prefetch-Aware Scheduling
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Solution Overview
Problem
Embedded DRAMs require refresh operations to maintain stored data, which introduce latency and clash with read/write accesses, increasing overall performance impact.
Innovation Solution
Implement 'look ahead' dynamic refreshes based on prefetch patterns, separating DRAM into sub-arrays for parallel refresh operations, and using a priority controller to manage refresh priorities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed in embedded DRAM, then data integrity is maintained, but latency increases and performance deteriorates
Solution Approach 1:
The DRAM array is divided into multiple subarrays, each with independent refresh control. This segmentation allows different subarrays to be refreshed at different times, enabling parallel refresh operations that reduce overall latency while maintaining data integrity across all subarrays.
Solution Approach 2:
The system performs 'look-ahead' dynamic refreshes by predicting future access patterns and refreshing data in advance before it is actually needed. This preliminary action ensures data integrity is maintained while allowing current access operations to proceed without latency penalties.
2Reliability
If refresh operations are prioritized over read/write accesses, then data is restored before loss, but read/write operations experience increased latency
Solution Approach 1:
The refresh controller dynamically adjusts refresh priorities based on real-time access patterns and data age. Instead of static prioritization, the system adaptively determines which subarrays require immediate refresh and which can be deferred, allowing read/write operations to proceed with minimal interruption while ensuring critical data is restored.
Solution Approach 2:
The system uses access pattern detection to automatically identify which data is likely to be accessed soon and prioritizes refreshing those subarrays. This self-service mechanism allows the refresh controller to make intelligent decisions about data restoration priorities without external intervention, balancing reliability and productivity automatically.
3Loss of time
If dynamic refreshes are performed based on prefetch patterns, then latency is reduced through parallel operations, but device complexity increases
Solution Approach 1:
The refresh controller is designed to perform multiple functions: it detects access patterns, generates dynamic refresh schedules, manages subarray prioritization, and coordinates parallel refresh operations. This multi-functional design consolidates complexity into a single controller unit rather than requiring separate control logic for each function, reducing overall system complexity while enabling latency reduction through parallel operations.
Data Source
AI summary
A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.