Embedded ECC Address Mapping in DRAM Pages
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Solution Overview
Problem
High-volume electronic devices require reliable memory solutions with embedded Error Correction Code (ECC) features, but adding ECC bits incurs significant overhead, which is not acceptable in cost-sensitive applications like smartphones, while high-reliability is needed in server markets.
Innovation Solution
Implementing ECC bits within the same DRAM page as data, using a common activation command to save power and reduce latency, and employing Partial Array Self Refresh techniques to minimize standby power consumption by allocating low-power modes to a small DRAM portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC bits are added to memory devices, then reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent merges data bits and ECC bits into the same memory page structure, where ECC bits are embedded within the page rather than being stored separately. This integration reduces the overhead by eliminating redundant memory structures while maintaining the reliability benefits of error correction code.
2Reliability
If ECC features are implemented in memory devices, then reliability is improved, but cost increases
Solution Approach 1:
The patent implements a universal memory page structure that can accommodate both data and ECC bits within the same page framework. This multi-functional approach allows the same memory infrastructure to serve both storage and error correction purposes, reducing the need for additional specialized components and lowering manufacturing costs.
3Use of energy by moving object
If ECC bits are embedded in the same DRAM page, then power consumption is reduced, but address mapping complexity increases
Solution Approach 1:
The patent segments the memory address space into distinct data regions and ECC regions within the same page, using separate address mapping logic for each segment. This segmentation allows the memory controller to selectively activate only the necessary portions of the page, reducing power consumption while managing address mapping complexity through structured organization.
Solution Approach 2:
The patent introduces an intermediary address mapping mechanism that translates logical addresses to physical locations within the unified page structure. This intermediary layer handles the complexity of mapping between data and ECC bits, shielding the rest of the system from the underlying complexity while enabling efficient power management.
Data Source
AI summary
Apparatus, systems, and methods to embed ECC data with cacheline data in a memory page are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive a request to read or write data to a memory device, wherein the data is mapped to a memory page comprising a plurality of cache lines, displace at least a portion of the plurality of cache lines to embed error correction code information with the data, and remap the portion of the plurality of cache lines to another memory location, and retrieve or store the data and the error correction code information on the memory page. Other embodiments are also disclosed and claimed.