Embedded EEPROM Cell with Symmetrical High-Voltage MOS
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Solution Overview
Problem
Conventional EEPROM structures with row/column decoders and selection transistors are inefficient and costly for applications requiring small capacity storage, such as LCD drivers and oscillator frequency control, where only a few dozen bytes of storage are needed.
Innovation Solution
An embedded EEPROM cell design featuring a writing unit with a flash cell MOS and a high-voltage MOS with symmetrical structure, along with a sensing unit using low-voltage sensing MOSs, which reduces area requirements and eliminates the need for a separate sense amplifier and decoding device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a row/column decoder and selection transistor are used for read/write access in conventional EEPROM structures, then the EEPROM can achieve proper read/write functionality, but the manufacturing cost and device complexity increase significantly
Solution Approach 1:
The patent merges the sensing function directly into the memory cell structure by using the drain of the flash cell MOS as the sensing node. The sensing unit shares the word line and bit line with the writing unit, eliminating the need for separate sense amplifiers and row/column decoders. This integration reduces device complexity while maintaining read/write functionality.
Solution Approach 2:
The flash cell MOS transistor serves multiple functions: it acts as both the storage element and the sensing element. The same transistor structure used for writing data also serves as the sensing unit during read operations, eliminating the need for separate dedicated sensing components and reducing overall device complexity.
2Ease of operation
If a row/column decoder and selection transistor are used in conventional EEPROM structures, then proper access control is achieved, but the manufacturing cost increases
Solution Approach 1:
The patent combines the access control function with the basic memory cell structure. The flash cell MOS transistor and its drain connection to the bit line provide inherent selection and sensing capabilities, eliminating the need for separate row/column decoders and selection transistors that would increase manufacturing complexity and cost.
Solution Approach 2:
The patent extracts and eliminates unnecessary components (row/column decoders, separate selection transistors, dedicated sense amplifiers) from the conventional EEPROM structure, retaining only the essential flash cell MOS transistor and its direct connections to achieve access control functionality.
3Ease of operation
If a conventional EEPROM structure with separate sense amplifier is used, then sensing functionality is achieved, but the area occupied by the device increases
Solution Approach 1:
The patent merges the sensing function into the memory cell itself by using the drain of the flash cell MOS as the sensing node. The sensing unit shares the word line and bit line with the writing unit, eliminating the need for separate sense amplifiers and reducing the overall device area significantly.
Solution Approach 2:
The flash cell MOS transistor structure serves its own sensing function through its drain connection to the bit line. The transistor structure itself provides the sensing capability without requiring external dedicated sensing components, achieving self-service functionality that reduces device area.
Data Source
AI summary
The EEPROM cell includes a writing unit having a flash cell Metal Oxide Semiconductor (MOS) for receiving from outside a gate selection signal via a gate and a drain selection signal via a drain, and writing one bit data, and a high-voltage MOS whose source is connected to a source of the flash cell MOS to have a symmetrical structure and for receiving the gate selection signal via a gate, and a sensing unit having a first sensing MOS whose source is connected to a power supply voltage, gate to a drain of a second sensing MOS and drain to the drain of the flash cell MOS, and the second sensing MOS whose source is connected to the power supply voltage, gate to the drain of the first sensing MOS and drain to the drain of the high-voltage MOS.