Embedded eFuse Structures in CMOS Metal Gate Technology

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Solution Overview

Problem

Conventional poly fuses and resistors are not compatible with gate-last high-k/metal gate technology due to damage from etching processes, particularly affecting nitride materials on metal gate structures.

Innovation Solution

Forming metal gates with a capping material, protecting them during etching to create a recess in dielectric material, and depositing insulator and metal materials within the recess to form electrical fuses or resistors in direct contact with a contact structure, ensuring the capping material remains intact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional poly fuses/resistors are formed using etching processes, then the fuses can be created, but the nitride material on metal gate structures becomes damaged

Engineering Contradiction:

Improveintegrity of nitride materialVSAvoidcompatibility with gate-last high-k/metal gate technology

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The invention segments the manufacturing process by forming fuses and resistors in separate recesses within the interlevel dielectric layer, away from metal gate structures. This spatial segmentation prevents etching damage to nitride materials on metal gates while enabling independent formation of fuse and resistor structures using standard etching processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention introduces an intermediary approach by using selective etching processes that target specific dielectric regions without affecting metal gate structures. The etching process is mediated to occur only in designated fuse/recess areas, protecting the nitride capping layers on metal gates from damage while still enabling fuse formation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If etching processes are used to form fuses, then fuse structures can be created, but damage occurs to nitride material on metal gates

Engineering Contradiction:

Improvefuse structure formationVSAvoidetching damage to nitride material

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The invention applies local quality by creating localized recesses in the interlevel dielectric layer at specific positions away from metal gate structures. The etching process is applied locally to these designated areas only, ensuring precise fuse formation while leaving nitride materials on metal gates unaffected. Each region has different properties: fuse regions receive etching, while metal gate regions are protected.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If fuses are formed close to metal gate structures, then space is saved, but the nitride capping material becomes damaged during etching

Engineering Contradiction:

Improvelayout space utilizationVSAvoidintegrity of capping material

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The invention resolves the spatial conflict by utilizing the vertical dimension and lateral positioning within the interlevel dielectric layer. Instead of placing fuses adjacent to metal gates in the same horizontal plane, the solution embeds fuses in recesses at controlled distances from gate structures. This dimensional arrangement maintains compact layout while preventing etching damage through proper spatial separation.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for the reliable formation of electrical fuses and resistors embedded in middle-of-line interlevel dielectric layers, preventing copper diffusion and ensuring compatibility with current CMOS integration processes, thereby improving the reliability and feasibility of semiconductor structures.

Implementation Method 1

forming a mask over the capping material of the metal gate structures; recessing the dielectric material between the metal gate structures by an etching process while the mask over the capping material protects the capping material and the metal gate structures

Methodology Applied

Scientific EffectPhysical barrier protection:

Implementation Method 2

recessing the dielectric material between the metal gate structures by an etching process

Methodology Applied

Scientific EffectEtching:

Implementation Method 3

depositing insulator material and metal material within the recess in the dielectric material

Methodology Applied

Scientific EffectMaterial deposition: Deposition (physical)

Implementation Method 4

forming a contact in direct electrical contact with the metal material

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10396027B2Electrical fuse and/or resistor structures

Publication Date: 2019.08.27 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.