Embedded ELD DAC Sharing in SAR Quantizers for Low-Power CTDS ADCs
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Solution Overview
Problem
Successive Approximation Register (SAR) ADCs used in Continuous Time Delta Sigma (CTDS) ADCs require low power but are relatively slow, necessitating the use of excess loop delay (ELD) compensation DACs to address conversion delay, which increases power and area consumption.
Innovation Solution
Embedding an excess loop delay (ELD) DAC within the SAR ADC, allowing for partial sharing of DAC units to minimize total DAC units while maintaining operational flexibility, and using capacitance ratios to control gain and compensate for loop delay without external reference voltage tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an ELD DAC is added to compensate for SAR conversion delay, then conversion speed is improved, but power consumption and area increase
Solution Approach 1:
The patent combines the ELD DAC and SAR ADC DAC into a single shared DAC structure. The ELD DAC and SAR ADC DAC share common capacitor units (specifically, the least significant bit capacitors), allowing both functions to operate with a unified hardware resource rather than separate independent DACs, thereby reducing overall power consumption and area while maintaining conversion speed improvement
Solution Approach 2:
The shared DAC units serve dual purposes: they function as part of the SAR ADC DAC during the SAR conversion phase and as part of the ELD DAC during the excess loop delay compensation phase. This multi-functionality allows the same hardware to support both the speed-critical ELD compensation and the normal SAR conversion operations without requiring separate dedicated components for each function
2Speed
If an ELD DAC is added to compensate for SAR conversion delay, then conversion speed is improved, but area consumption increases
Solution Approach 1:
The patent merges the ELD DAC and SAR ADC DAC into a single shared DAC structure. The ELD DAC and SAR ADC DAC share common capacitor units (specifically, the least significant bit capacitors), allowing both functions to operate with a unified hardware resource rather than separate independent DACs, thereby reducing overall power consumption and area while maintaining conversion speed improvement
Solution Approach 2:
The ELD DAC functionality is nested within the SAR ADC DAC structure by embedding the ELD DAC capacitors as a subset of the SAR ADC DAC capacitor array. Specifically, the LSB capacitors of the SAR ADC DAC are reused as the MSB capacitors of the ELD DAC, creating a nested hierarchical relationship where one DAC structure contains and shares resources with another, minimizing total area occupation
3Adaptability or versatility
If separate DAC units are used for ELD DAC and SAR ADC DAC, then operational flexibility is maintained, but device complexity increases
Solution Approach 1:
The patent implements dynamic switching between different operational modes of the shared DAC. Control logic dynamically selects whether the shared capacitor units are connected to the SAR ADC input or the ELD feedback path based on the conversion phase, allowing the system to adapt its configuration in real-time without requiring physically separate static components for each function
Solution Approach 2:
The DAC capacitor array is segmented into different functional groups that can be independently controlled: most significant bit capacitors dedicated to SAR ADC operation, least significant bit capacitors shared with ELD DAC, and intermediate capacitors that can be dynamically allocated. This segmentation allows operational flexibility while reducing overall complexity compared to completely separate DAC structures
Data Source
AI summary
Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.