Embedded Encoder Decoder for Memory Touchup
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Solution Overview
Problem
Traditional low power cell touchup techniques in memory devices are interface bandwidth, controller, and power intensive due to the need for data transfer between the memory sub-system controller and the memory device, which degrades data reliability over time due to charge loss.
Innovation Solution
Embedding an encoder, decoder, and buffer within the memory device allows for local touchup operations, eliminating the need for data transfer over the interface and reducing power consumption by performing corrections and reprogramming internally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional low power cell touchup techniques are used with external encoder/decoder, then data reliability can be maintained, but controller resource consumption increases and interface bandwidth is degraded
Solution Approach 1:
The encoder and decoder functionality is extracted from the memory sub-system controller and relocated to the memory device itself. This extraction eliminates the need for data transfer between controller and memory device during touchup operations, reducing controller resource consumption and interface bandwidth requirements while maintaining data reliability through embedded error correction capabilities
Solution Approach 2:
The memory device is equipped with embedded encoder and decoder circuits that enable it to perform self-correction of low power cells without external controller intervention. The memory device reads its own data, performs decoding to identify errors, corrects the errors, and reprograms the cells autonomously, eliminating dependency on controller resources and interface bandwidth
2Reliability
If traditional low power cell touchup techniques are used with data transfer over interface, then corrections can be performed, but power consumption increases
Solution Approach 1:
The power-intensive data transfer operation is eliminated by extracting the correction functionality to the memory device. The embedded encoder/decoder performs all correction operations locally without requiring data to be transferred over the interface, dramatically reducing power consumption while maintaining the ability to correct low power cells
Solution Approach 2:
The memory device performs self-correction of low power cells using its own embedded encoder and decoder circuits. By reading data internally, performing decoding and correction locally, and reprogramming cells without external communication, the system eliminates the power consumption associated with interface data transfer while maintaining data reliability
3Reliability
If data transfer between controller and memory device is performed for touchup, then corrections can be made, but interface bandwidth is consumed
Solution Approach 1:
The data transfer requirement is eliminated by extracting the correction functionality to the memory device. The embedded encoder/decoder performs all touchup operations internally without requiring data to traverse the interface, freeing up interface bandwidth for other operations while maintaining data reliability through local error correction
Solution Approach 2:
The memory device autonomously performs read, decode, correct, and reprogram operations using its own embedded encoder and decoder. This self-service approach eliminates all data transfer over the interface during touchup operations, maximizing interface bandwidth availability for host operations while maintaining data reliability
Data Source
AI summary
Data is read from a set of memory cells of a memory device to a buffer of the memory device. One or more bits in error in the data stored by the buffer are corrected by a decoder of the memory device. The decoder corrects the one or more bits in error by decoding the data stored by the buffer. The decoding of the data results in corrected data. An encoder of the memory device encodes the corrected data and the encoded corrected data is programmed to the set of memory cells.


