Embedded Epitaxial Fin Structure for Low-Leakage GAA Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing efficiency.
Innovation Solution
The process involves forming fin structures and gate all-around (GAA) transistor structures using double-patterning or multi-patterning techniques, including the use of sacrificial layers, spacers, and epitaxial growth to create fin structures and channel structures with precise patterning and etching, allowing for smaller pitches and improved etching selectivity, and the integration of embedded epitaxial structures to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the fabrication process into multiple patterning steps (e.g., self-aligned double patterning, self-aligned triple patterning) where each step creates a portion of the final pattern. This allows complex small-geometry structures to be formed through sequential simpler steps, managing fabrication complexity while achieving high functional density
Solution Approach 2:
The patent employs preliminary action through self-aligned processes where sacrificial layers and spacer structures are formed in advance to define subsequent pattern locations. These preliminary structures guide the formation of final device features, enabling precise patterning at small dimensions while simplifying the overall fabrication sequence
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent applies local quality by forming regions with different materials and properties in specific locations, such as embedded epitaxial structures with different compositions in source/drain regions, and selective doping profiles. This allows optimization of local device performance and reliability while maintaining small overall feature sizes for high density
Solution Approach 2:
The patent employs beforehand cushioning through the formation of sacrificial layers and spacer structures that protect critical regions during fabrication. These preliminary structures cushion against process variations and damage, ensuring reliable pattern transfer and structure formation at small dimensions
3Reliability
If embedded epitaxial structures are formed on fin structures, then current flow is improved and current leakage is reduced, but device fabrication complexity increases
Solution Approach 1:
The patent applies the nested doll principle by forming embedded epitaxial structures that are integrated within and around the fin structure. The epitaxial layers are grown in-situ on the fin surfaces, creating a nested configuration where the fin structure is embedded within the broader device architecture, improving current flow without requiring separate discrete components
Solution Approach 2:
The patent merges the fin structure formation with epitaxial growth in a unified process sequence. The same epitaxial reactor and growth conditions used to create the fin structures are leveraged to form the embedded epitaxial source/drain regions, combining multiple device features into a single integrated fabrication flow that reduces overall complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices with improved current flow and reduced risk of current leakage, while also simplifying the fabrication process by allowing for smaller feature sizes and enhanced device performance.
Implementation Method 1
forming a first epitaxial structure on the fin structure and forming a second epitaxial structure on the exposed side surface of the lower portion of the fin structure
Data Source
AI summary
A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.