Embedded Epitaxial Transistor Structure for GIDL Mitigation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The reduction in sidewall spacer thickness in semiconductor transistors leads to gate-induced drain leakage current (GIDL) issues in medium-voltage transistors, and existing devices occupy a large chip area, necessitating improvements in transistor structure.

Innovation Solution

Incorporation of undoped or doped epitaxial SiGe or SiP layers in the drain and source regions of the transistor structure, with specific placement and thickness relative to the junction depth, and the use of silicide layers without direct contact, along with trench isolation and sidewall spacers, to enhance performance and reduce chip area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the sidewall spacer thickness is reduced to enable smaller transistor size, then the chip area is reduced, but gate-induced drain leakage current (GIDL) problems occur

Engineering Contradiction:
Improvechip areaVSAvoidgate-induced drain leakage current
Core Design Contradiction:
Area of moving objectVSObject-generated harmful factors

Solution Approach 1:

An embedded epitaxial structure is introduced as an intermediary layer between the drain LDD region and the heavily doped drain region. This intermediate structure mitigates the direct interaction that causes GIDL, allowing reduced sidewall spacer thickness without suffering from leakage current problems.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The embedded epitaxial structure is selectively placed only in the drain LDD region where GIDL occurs, rather than uniformly throughout the device. This localized modification addresses the specific problem area while maintaining other device characteristics.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the embedded medium-voltage transistor device is fabricated with conventional structure, then the device can be manufactured, but it occupies a large chip area

Engineering Contradiction:
Improvedevice manufacturabilityVSAvoidchip area
Core Design Contradiction:
Ease of manufactureVSArea of moving object

Solution Approach 1:

The embedded epitaxial structure adds a vertical dimension to the device architecture by inserting a distinct layer between existing horizontal structures. This vertical modification enables shorter gate length and reduced chip area without compromising manufacturability, as the structure can be integrated into existing fabrication processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure effectively mitigates GIDL and allows for a shorter gate length, reducing the chip area occupied by medium-voltage transistors while maintaining performance.

Implementation Method 1

A first embedded epitaxial structure is formed in the drain LDD region and between the gate structure and the heavily doped drain region. The first embedded epitaxial structure comprises an undoped epitaxial SiGe layer or an undoped epitaxial SiP layer.

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

the semiconductor transistor structure further includes a drain silicide layer disposed on the heavily doped drain region

Methodology Applied
Scientific EffectSilicide formation: Deposition (physical)

Data Source

PatentUS20250331218A1Semiconductor transistor structure and fabrication method thereof
Publication Date: 2025.10.23 UNITED MICROELECTRONICS CORP
  • US20250331218A1 patent drawing
  • US20250331218A1 patent drawing
  • US20250331218A1 patent drawing

AI summary

A semiconductor transistor structure includes a substrate; an active region located on the substrate and surrounded by a trench isolation region; a source structure located in the active region, including a source LDD region and a heavily doped source region; a drain structure located in the active region and spaced apart from the source structure, wherein the drain structure includes a drain LDD region and a heavily doped drain region; a gate structure located on the active region and between the source structure and the drain structure; and a first embedded epitaxial structure disposed in the drain LDD region and located between the gate structure and the heavily doped drain region.