Embedded Fan-Out Package Substrate for High I/O Without Multilayer Complexity
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Solution Overview
Problem
Conventional flip-chip semiconductor package structures face challenges in miniaturization, high functionality, and cost-effectiveness due to complex multilayer interconnects, which increase manufacturing costs and reduce yield and reliability.
Innovation Solution
A semiconductor package structure incorporating a fan-out wafer-level package with an embedded-type package substrate and a Redistribution Layer (RDL) as a fan-out layer, reducing the number of interconnect layers and mitigating warpage, thereby simplifying the substrate structure and lowering costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a complicated multilayer interconnect structure is formed in the package substrate to respond to the increase in I/O pads, then the I/O pad capacity is improved, but the dimensions and manufacturing cost of the package substrate are greatly increased while the yield is reduced
Solution Approach 1:
The package substrate structure is segmented into multiple functional layers including an organic substrate layer, a first interconnect layer with through-vias, and a second interconnect layer with redistribution patterns. This segmentation allows I/O pads to be distributed across multiple layers, increasing capacity while keeping each individual layer relatively simple and manufacturable.
Solution Approach 2:
The patent utilizes vertical stacking of interconnect layers to increase I/O pad capacity. By redistributing pads across multiple z-dimensions (layers) rather than only expanding in the x-y plane, the effective pad capacity increases while the footprint of the substrate remains controlled.
2Adaptability or versatility
If a complicated multilayer interconnect structure is formed in the package substrate, then the I/O pad capacity is improved, but the manufacturing cost of the semiconductor package structure goes up
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the organic substrate, creating through-vias, depositing first interconnect layer, forming second interconnect layer, and adding protective layers. This segmentation allows each step to be optimized independently and performed by specialized equipment, reducing overall manufacturing cost while achieving high I/O capacity.
Solution Approach 2:
The organic substrate is prepared in advance with through-vias formed before the interconnect layers are deposited. This preliminary action allows for better process control and yields, reducing rework and scrap costs while enabling the complex multilayer structure to be built efficiently.
3Adaptability or versatility
If a complicated multilayer interconnect structure is formed in the package substrate, then the I/O pad capacity is improved, but the reliability and yield of the semiconductor package structure are reduced
Solution Approach 1:
Protective layers are formed over the interconnect structures before subsequent processing steps. These protective layers cushion and protect the delicate interconnect patterns and through-vias from damage during manufacturing, reducing defects and improving yield while enabling the complex multilayer structure to be reliably fabricated.
Solution Approach 2:
The complex interconnect structure is divided into manageable layers with through-vias providing mechanical and electrical continuity. This segmentation reduces stress concentration and allows for better defect isolation, improving overall reliability and yield compared to a monolithic complex structure.
Data Source
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AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.