Embedded Fan-Out Conductive Layer for Peel-Resistant Packaging

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Solution Overview

Problem

The existing fan-out structures in semiconductor device packages with narrow conductive layers traversing long distances are prone to peeling off during formation, disrupting the connection between embedded semiconductor dies and motherboards.

Innovation Solution

The implementation of a semiconductor device package with a dielectric layer, an electronic component, and a conductive element where the conductive layer is embedded within the dielectric layer and has an exposed portion, reducing the risk of peeling by minimizing the surface area exposed during the flash etch process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a fan-out structure with a narrow conductive layer is used to connect embedded semiconductor die with motherboard, then the pitch of embedded semiconductor die can be reduced, but the conductive layer may be peeled off during formation

Engineering Contradiction:
Improvepitch of embedded semiconductor dieVSAvoidpeeling resistance of conductive layer
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The conductive layer is transitioned from a surface-level structure to an embedded structure within the dielectric layer. This dimensional change embeds the conductive layer in the third dimension (depth), providing mechanical support from the surrounding dielectric material and preventing peeling during the formation process while maintaining narrow pitch dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive layer is nested within the dielectric layer, creating a protected internal structure. The dielectric material surrounds and supports the conductive layer, similar to nested dolls, providing structural integrity and preventing the conductive layer from peeling off during manufacturing processes.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the conductive layer is embedded in the dielectric layer, then the risk of peeling is reduced, but the connection length increases

Engineering Contradiction:
Improvepeeling resistance of conductive layerVSAvoidconnection length of conductive layer
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The conductive layer is changed from a narrow, surface-level trace to a broader, embedded structure within the dielectric layer. This parameter change in geometry and positioning allows the conductive layer to maintain electrical connection functionality while gaining mechanical support from the surrounding dielectric material, preventing peeling without proportionally increasing connection length.

Inventive Principle:
Principle #35Parameter changes

3Area of moving object

If a narrow conductive layer traverses a long distance, then the pitch can be reduced, but the conductive layer is more prone to damage during formation

Engineering Contradiction:
Improvepitch of embedded semiconductor dieVSAvoiddamage susceptibility of conductive layer
Core Design Contradiction:
Area of moving objectVSObject-affected harmful factors

Solution Approach 1:

The conductive layer is positioned in a different dimension by embedding it within the dielectric layer rather than placing it on the surface. This dimensional relocation protects the narrow, long-distance conductive path from mechanical damage during formation processes while maintaining the required pitch dimensions for high-density packaging.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dielectric layer serves as a protective cushion surrounding the conductive layer before any damage can occur. This pre-existing protective structure absorbs mechanical stresses and prevents damage to the narrow conductive layer during the formation process, enabling long-distance connections without increased susceptibility to harm.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11830799B2Semiconductor device package, antenna device, and method for manufacturing the same
Publication Date: 2023.11.28 ADVANCED SEMICON ENG INC
  • US11830799B2 patent drawing
  • US11830799B2 patent drawing
  • US11830799B2 patent drawing

AI summary

A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a dielectric layer, an electronic component, a first conductive layer, and a conductive element. The dielectric layer has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the dielectric layer. The first conductive layer is embedded in the dielectric layer and adjacent to the first surface of the dielectric layer. The conductive element is disposed on the first surface of the dielectric layer and in contact with the first conductive layer.