Embedded FeDRAM with Independent Plate Lines and Metal Straps
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Solution Overview
Problem
Conventional embedded FeDRAM architectures face challenges in reducing bit-cell disturbs and simplifying the read/write process, which are essential for improving memory performance and efficiency.
Innovation Solution
The integration of a 2D array of metal-ferroelectric-metal (MFM) capacitors with independent plate lines and access transistors, where separate plate lines are used to reduce top capacitor plate series resistance and write disturbs, and metal straps are employed as electrical shunts to minimize electric resistance across capacitor conductors, allowing for independent biasing of capacitor plate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional embedded FeDRAM architectures are used, then the memory structure is simpler, but bit-cell disturbs increase and read/write process becomes more complex
Solution Approach 1:
The capacitor plate lines are segmented into separate top and bottom plate lines, allowing independent control and biasing. This segmentation enables reduced bit-cell disturbs by independently managing the electrical states of each plate, while the segmented lines are strategically routed to minimize interference with adjacent bit-cells.
Solution Approach 2:
Metal straps are strategically placed at specific locations (e.g., at corners or along edges of capacitor arrays) to provide localized electrical shunting. This creates regions of reduced resistance exactly where needed to minimize bit-cell disturbs during read/write operations, rather than uniformly increasing conductivity throughout the entire structure.
2Object-generated harmful factors
If separate plate lines are used, then write disturbs are reduced, but device complexity increases
Solution Approach 1:
The interconnect structure is segmented into separate top and bottom plate lines that can be independently routed and controlled. This allows write disturbs to be minimized by independently managing the electrical states of each plate, while the segmented lines are strategically routed to reduce interference with adjacent bit-cells.
Solution Approach 2:
Metal straps serve as intermediary elements that electrically shunt the separate plate lines, reducing series resistance without requiring fully independent interconnect structures for each plate. The straps act as mediators that connect multiple capacitor plates while minimizing resistance and write disturbs.
3Reliability
If metal straps are employed, then electric resistance is minimized, but manufacturing complexity increases
Solution Approach 1:
Metal straps are strategically placed at specific locations (e.g., at corners or along edges of capacitor arrays) to provide localized electrical shunting. This creates regions of reduced resistance exactly where needed to minimize bit-cell disturbs during read/write operations, rather than uniformly increasing conductivity throughout the entire structure.
Solution Approach 2:
The metal straps are integrated with existing interconnect layers and capacitor structures, merging the resistance-reduction function with the existing manufacturing process flow. The straps are formed using standard metallization techniques that are already part of the backend-of-line process, avoiding the need for entirely new fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces bit-cell disturbs and simplifies the read/write process, enhancing the performance and efficiency of embedded memory by minimizing electric resistance and allowing for independent control of capacitor plate lines.
Implementation Method 1
each capacitor comprises a ferroelectric material. An embedded memory architecture may then rely on polarization states of a capacitor's ferroelectric material, which can be changed when an electric field applied across the capacitor conductors is of correct polarity and sufficient strength to alter the semi-permanent dipoles within the ferroelectric material.
Implementation Method 2
metal straps are employed as electrical shunts to minimize electric resistance across capacitor conductors
Data Source
AI summary
Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.