Embedded FeRAM Nested Electrode Layout With Fewer Photomasks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity and cost of forming embedded flash memory in integrated chips are high due to the need for a large number of masks in the fabrication process.
Innovation Solution
The formation of an embedded FeRAM device with a nested electrode using a replacement process that simplifies the fabrication by reducing the number of photomasks required, allowing for efficient and low-cost production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded flash memory is formed using conventional fabrication processes, then non-volatile memory functionality is achieved, but the number of photomasks required increases fabrication complexity and cost
Solution Approach 1:
The patent implements a nested electrode structure where a first electrode is positioned within a first recess and a second electrode is positioned within a second recess, with both electrodes nested within the ferroelectric layer. This nested configuration allows the FeRAM device to achieve complex three-dimensional functionality while reducing the number of photomasks required during fabrication, as the nested structure can be formed through sequential deposition and patterning steps rather than requiring separate masks for each electrode layer.
Solution Approach 2:
The patent transitions from planar electrode structures to three-dimensional nested electrode structures by creating recesses in the ferroelectric layer and positioning electrodes within these recesses. This dimensional change allows for increased storage density and functionality without proportionally increasing the number of photomasks, as the vertical nesting utilizes the third dimension (depth) rather than requiring additional lateral patterning steps.
2Ease of manufacture
If embedded FeRAM device with nested electrode is formed using replacement process, then fabrication cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a replacement process where sacrificial structures are formed first, then removed to create cavities for the nested electrodes. This preliminary action allows the ferroelectric layer to be deposited over the sacrificial structures, and after sacrificial structure removal, the electrodes are formed in the resulting cavities. This sequence simplifies the overall fabrication process and reduces cost while the precise positioning is achieved through the original sacrificial structure geometry.
Solution Approach 2:
The patent uses sacrificial structures as intermediary elements during fabrication. These sacrificial structures serve as temporary placeholders that define the eventual electrode positions and geometries. The sacrificial structures are formed with precise dimensions, then removed to create cavities, and finally replaced with the actual electrodes. This intermediary approach allows cost-effective fabrication while maintaining precise electrode positioning through the sacrificial structure template.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of embedded FeRAM devices using 10%-30% of the photomasks used in embedded flash fabrication, resulting in a cost-effective and efficient method for integrating FeRAM devices into integrated chips.
Implementation Method 1
FeRAM devices are one promising candidate for a next generation non-volatile memory technology. This is because FeRAM devices provide for many advantages, including a fast write time, high endurance, low power consumption, and low susceptibility to damage from radiation.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A ferroelectric material is arranged over the substrate and between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the ferroelectric material. The isolation structure has a first width measured along an uppermost surface of the isolation structure and a second width measured along a horizontal line below the uppermost surface of the isolation structure. The second width is larger than the first width.