Embedded FeRAM Nested Electrode Structure for Low-Cost Integration
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Solution Overview
Problem
The complex and costly fabrication process of embedded flash memory in integrated chips hinders efficient and cost-effective integration of ferroelectric random-access memory (FeRAM) devices, which are promising for next-generation non-volatile memory technology due to their fast write times, high endurance, and low power consumption.
Innovation Solution
A simplified fabrication process for embedded FeRAM devices using a replacement method that forms a nested structure with a ferroelectric layer and conductive electrode, reducing the number of photomasks required and allowing integration with logic devices on the same chip without impacting their performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If embedded flash memory fabrication process is used, then memory integration is achieved, but fabrication complexity and cost increase
Solution Approach 1:
The patent implements a nested electrode structure where a first electrode is positioned within a recess of a ferroelectric layer, which itself is within a memory cavity. This nesting approach consolidates multiple structural elements into a compact configuration, reducing the number of separate fabrication steps and photomasks required compared to conventional embedded flash memory processes.
Solution Approach 2:
The fabrication process integrates FeRAM device formation with standard CMOS logic device manufacturing steps. The same deposition and etching processes used for logic devices are utilized for memory device formation, allowing single-chip integration without requiring separate dedicated fabrication lines or additional complex process modules.
2Use of energy by moving object
If conventional memory structures are used, then fabrication is simpler, but power consumption increases due to longer interconnects
Solution Approach 1:
The nested electrode configuration places the first electrode directly within the ferroelectric layer recess, minimizing the horizontal distance between memory and logic device interconnects. This reduced interconnect length directly lowers resistive power losses while the nested structure itself adds minimal fabrication complexity.
Solution Approach 2:
The patent transitions from planar electrode arrangements to a three-dimensional nested configuration. By positioning electrodes vertically within recesses rather than only laterally adjacent, the design achieves shorter current paths and reduced RC delays without significantly increasing lateral footprint or fabrication step count.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.