Embedded FeRAM Nested Electrode Structure for Low-Mask Integration
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Solution Overview
Problem
The complexity and cost of forming embedded flash memory in integrated chips due to the need for a large number of masks in the fabrication process, which increases the complexity and expense of production.
Innovation Solution
The integration of a ferroelectric random-access memory (FeRAM) device with a nested electrode structure, formed using a replacement process that reduces the number of photomasks required, allowing for a simpler and more efficient fabrication process, with the FeRAM device being embedded within a recessed region of the chip to avoid impacting logic devices and reduce fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded flash memory is formed using traditional fabrication processes, then non-volatile memory functionality is achieved, but the number of photomasks required increases fabrication complexity and cost
Solution Approach 1:
The patent implements a nested electrode structure where a first electrode is positioned within a recess of a ferroelectric layer, and a second electrode is positioned within a recess of a capping layer. This nesting approach consolidates multiple memory cell components into a compact three-dimensional arrangement, enabling FeRAM functionality with reduced fabrication complexity compared to traditional planar flash memory processes
Solution Approach 2:
The patent changes the material parameter by using ferroelectric material instead of traditional flash memory materials. This parameter change enables the memory to achieve non-volatile functionality through the ferroelectric effect, where electric dipoles in the ferroelectric layer can be switched between stable states to store data, thereby achieving reliability without requiring the complex multi-mask flash memory fabrication process
2Reliability
If embedded flash memory is formed using traditional fabrication processes, then non-volatile memory functionality is achieved, but fabrication cost increases due to large number of masks
Solution Approach 1:
The nested electrode structure consolidates multiple memory cell components into a compact three-dimensional arrangement, enabling FeRAM functionality with reduced fabrication complexity and lower mask counts compared to traditional planar flash memory processes
Solution Approach 2:
The ferroelectric layer serves multiple functions: it acts as the memory element for data storage through its switchable polarization states, and it also functions as a dielectric layer in the capacitor structure. This multi-functionality reduces the need for separate dedicated layers, simplifying the overall fabrication process and reducing costs
3Adaptability or versatility
If FeRAM device is embedded in recessed region to avoid impacting logic devices, then integration is achieved, but device area is reduced
Solution Approach 1:
The patent embeds the FeRAM device within a recessed region of the substrate, nesting the memory structure into the substrate depth rather than occupying additional planar area. The first electrode is positioned within a recess of the ferroelectric layer, and the second electrode is positioned within a recess of the capping layer, creating a compact three-dimensional structure that integrates with logic devices without consuming excessive chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the low-cost fabrication of embedded FeRAM devices using 10-30% of the photomasks needed for embedded flash memory, while maintaining performance and reducing power consumption, thus addressing the cost and complexity issues of traditional embedded flash memory processes.
Implementation Method 1
FeRAM devices provide for many advantages, including a fast write time, high endurance, low power consumption, and low susceptibility to damage from radiation
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material.